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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Qi Guo Weiwu Hu Tianshi Chen Haihua Shen Yunji Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

As a primary method for functional verification of microprocessors, simulation-based verification has received extensive studies over the last decade. Most investigations have been dedicated to the generation of stimuli (test cases), while relatively few has focused on explicitly reducing the redundant stimuli among the generated ones. In this paper, we propose an on-the-fly approach for reducing the stimuli redundancy based on machine learning techniques, which can learn from new knowledge in every cycle of simulation-based verification. Our approach can be easily embedded in traditional framework of simulation-based functional verification, and the experiments on an industrial microprocessor have validated that the approach is effective and efficient.

关键词： Functional Verification Stimuli Reduction Redundancy Online Learning Godson-2

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A 680 V LDMOS on a thin SOI with an improved field oxide structure and dual field plate

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Journal of Semiconductors 2012年第5期33卷 44-47页

作者：王中健程新红夏超徐大伟曹铎宋朝瑞俞跃辉沈达身 State Key Laboratory of Functional Materials for Informatics Shanghai Institute of Micro-System&Information TechnologyChinese Academy of Sciences Graduate University of the Chinese Academy of Sciences Department of Electrical and Computer Engineering University of Alabama in Huntsville

A 680 V LDMOS on a thin SOI with an improved field oxide（FOX） and dual field plate was studied *** FOX structure was formed by an ＂oxidation-etch-oxidation＂ process,which took much less time to form,and had a low protrusion profile.A polysilicon field plate extended to the FOX and a long metal field plate was used to improve the specific *** optimized drift region implant for linear-gradient doping was adopted to achieve a uniform lateral electric *** a SimBond SOI wafer with a 1.5μm top silicon and a 3μm buried oxide layer,CMOS compatible SOI LDMOS processes are designed and implemented successfully. The off-state breakdown voltage reached 680 V,and the specific on-resistance was 8.2Ω·mm^2.

关键词： SOI LDMOS field oxide field plate breakdown voltage

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Software-Based Self-Testing of Processors Using Expanded Instructions

Software-Based Self-Testing of Processors Using Expanded Ins...

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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Ying Zhang Xiaowei Li Huawei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

In this paper, an automatic test instruction generation (ATIG) technique using expanded instructions is presented for software-based selftesting (SBST) of processors. First, mappings between expanded instructions and signals are obtained through data mining, and they are used to impose value ranges of expanded instructions on component signals and generate instruction-level constraints. Second, virtual circuits are established based on the instruction-level constraints, and test patterns are generated for the constrained components. Third, test patterns are translated into test instructions according to the values of controlling signals and constraints for their mappings to instructions, and an SBST program is produced after assembling the test instructions. Experimental results on the Parwan processor show that the proposed ATIG technique can achieve 94.8％ stuck-at fault coverage, which is close to that of the full-scan test generation method. In addition, it can cut down 57％ test volume of the previous random pattern generation based SBST technique, while the test time reduces to one thirteenth of the previous SBST technique.

关键词： Software-Based Self-Test Automatic Test Instruction Generation Instruction-Level Constraint On-Line Test

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Generalized interface automata with multicast synchronization

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Frontiers of computer Science 2015年第1期9卷 1-14页

作者： Fei HE Xiaoyu SONG Ming GU Jiaguang SUN Tsinghua National Laboratory for Information Science and Technology (TNList) Tsinghua University Beijing 100084 China Key Laboratory for Information System Security Ministry of Education Beijing 100084 China School of Software Tsinghua University Beijing 100084 China Department of Electrical & Computer Engineering Portland State University Oregon 97207 USA

Interface automata are one of the prominent formalisms for specifying interface behaviors of componentbased systems. However, only one-to-one communication is allowed in the composition of interface automata. This paper presents multicast interface automata which generalize the classic interface automata and accommodate multicast communication mechanism. The multicast interface automata endorse both bottom-up and top-down design methodologies. Theoretical results on compatibility and refinement are established for incremental design and independent implementability.

关键词： interface automata multicast communication,component interaction verification

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CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors

CREA: A Checkpoint Based Reliable Micro-architecture for Sup...

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The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

作者： Shijian Zhang Weiwu Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

Conventional temporal redundant techniques to detect transient faults have resulted in considerable performance loss. One major reason for this problem is the reclamation of some critical resources, such as the instruction window and physical registers, is delayed, which degrades instruction-level parallelism. This paper proposes a novel fault- tolerant micro-architecture based on checkpoint mechanism. All occupied resources are reclaimed during the retirement stage in the first execution. Therefore, the performance overhead is mitigated evidently. Our scheme requires only small hardware cost and provides short fault detection latency.

关键词： Registers Fault detection Retirement Hardware Costs Delay Pipelines Buffer storage Redundancy Yarn

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Fault diagnosis of arbiter physical unclonable function 20

Fault diagnosis of arbiter physical unclonable function

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20th Design, Automation and Test in Europe, DATE 2017

作者： Ye, Jing Quo, Qingli Hu, Yu Li, Xiaowei State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China

ISBN: (纸本)9783981537093

Physical Unclonable Function (PUF) has broad application prospects in the field of hardware security. If faults happen in PUF during manufacturing, the security of whole chip will be threatened. Fault diagnosis plays an important role in the yield learning process. However, since different manufactured PUFs with the same design have different Challenge-Response Pairs (CRPs), which cannot be predicted, the traditional fault diagnosis method based on comparing the fault-free responses of a design and the failing responses of chips is no longer suitable for diagnosing PUF. Therefore, this paper proposes a fault diagnosis method toward classic arbiter PUF. The stuck-at faults and the delay faults are considered. Based on the expected uniformity of arbiter PUF, a diagnostic challenge generation method and a corresponding CRP analysis method are proposed to distinguish faults within the arbiter PUF. Experimental results show that the diagnostic accuracy achieves 100.0% with good diagnostic resolution. © 2017 IEEE.

关键词： Failure analysis

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Frequency Analysis Method for Propagation of Transient Errors in Combinational Logic

Frequency Analysis Method for Propagation of Transient Error...

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The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

作者： Shaohua Lei Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

The continuous development of VLSI technology is shrinking the minimal sizes to nanometer region, making circuits more susceptible to transient error. In this paper, we present a frequency analysis method to accurately estimate the possible propagation of transient fault-due glitches through a CMOS combinational circuit. We use the frequency feature of signal and frequency response of electrical system to analyze the propagation of transient error. Experiments show that on average, our approach provides approximately 95％ accuracy and several orders of magnitude faster with respect to HSPICE simulation.

关键词： Transient analysis Frequency estimation CMOS logic circuits Very large scale integration CMOS technology Circuit faults Combinational circuits Frequency response Signal analysis Circuit simulation

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OeIM: An optoelectronic interconnection middleware for the exascale computer 21

OeIM: An optoelectronic interconnection middleware for the e...

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21st IEEE International Conference on High Performance Computing and Communications, 17th IEEE International Conference on Smart City and 5th IEEE International Conference on Data Science and systems, HPCC/SmartCity/DSS 2019

作者： Shao, En Tan, Guangming Wang, Zhan Sun, Ninghui State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781728120584

During the improved process of hardware technology and program optimization in the high-performance computer (HPC), the overall computing ability of supercomputer increases correspondingly. As a large-scale system and a milestone to the HPC community shortly, the envisioned exascale computer will be comprised of nearly 5000 interconnected nodes and tens of thousands of computing nodes. Interconnection innovations in such a system are critical to improving overall computing ability. In this paper, we investigate optoelectronic interconnection in an exascale computer system design. Here, we propose a new software stack called Optoelectronic Interconnection Middleware (OeIM) to enable efficient utilization of the optical interconnection. OeIM allows for the use of two novel functions, namely the reconfigurable function and the running-time function. We evaluate OeIM using both communication benchmark (IMB) and real-world motif applications (Linpack, HPCG, and Graph500) in a prototyped exascale computer. The experiment shows that OeIM reduced latency by form 20 to 35% in the large-range communication, improved throughput by 30% in the long-distance communication, and improved the motif applications by more than 10%. Together, our results demonstrate that OeIM is an effective bridge between the optical switching device and system scheduler to improve communication capability. © 2019 IEEE.

关键词： Middleware

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Deep Reinforcement Agent for Failure-aware Job scheduling in High-Performance Computing 27

Deep Reinforcement Agent for Failure-aware Job scheduling in...

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27th IEEE International Conference on Parallel and Distributed systems, ICPADS 2021

作者： Yang, Kang Cao, Rongyu Zhou, Yueyuan Zhang, Jiawei Shao, En Tan, Guangming Institute of Computing Technology CAS State Key Laboratory of Computer Architecture Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665408783

Job scheduling is crucial in high-performance computing (HPC), which is dedicated to deciding when and which jobs are allocated to the system and placing the jobs on which resources, by considering multiple scheduling goals. Along with the incremental of various resources and dazzling deep learning training (DLT) workloads, job failure becomes a quite common issue in HPC, which will affect user satisfaction and cluster utilization. To alleviate the influence of hardware and software errors as much as possible, in this paper, we aim to tackle the problem of failure-aware job scheduling in HPC clusters. Inspired by the success of previous studies of deep reinforcement learning-driven job scheduling, we propose a novel HPC scheduling agent named FARS (Failure-aware RL-based scheduler) by considering the effects of job failures. On the one hand, a neural network is applied to map the information of raw cluster and job states to job placement decisions. On the other hand, to consider the influence of job failure for user satisfaction and cluster utilization, FARS leverages make-span of the entire workload as the training objective. Additionally, effective exploration and experience replay techniques are applied to obtain effectively converged agent. To evaluate the capability of FARS, we design extensive trace-based simulation experiments with the popular DLT workloads. The experimental results show that, compared with the best baseline model, FARS obtains 5.69% improvement of average make-span under different device error rates. Together, our FARS is an ideal candidate for failure-aware job scheduler in HPC clusters. © 2021 IEEE.

关键词： Scheduling

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Analysis and mitigation of function interaction risks in robot apps 21

Analysis and mitigation of function interaction risks in rob...

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24th International Symposium on Research in Attacks, Intrusions and Defenses, RAID 2021

作者： Xu, Yuan Zhang, Tianwei Bao, Yungang State Key Laboratory of Computer Architecture Institute of Computing Technology University of Chinese Academy of Sciences Peng Cheng Laboratory China Nanyang Technological University China

ISBN: (纸本)9781450390583

Robot apps are becoming more automated, complex and diverse. An app usually consists of many functions, interacting with each other and the environment. This allows robots to conduct various tasks. However, it also opens a new door for cyber attacks: adversaries can leverage these interactions to threaten the safety of robot operations. Unfortunately, this issue is rarely explored in past works. We present the first systematic investigation about the function interactions in common robot apps. First, we disclose the potential risks and damages caused by malicious interactions. By investigating the relationships among different functions, we identify and categorize three types of interaction risks. Second, we propose RTron, a novel system to detect and mitigate these risks and protect the operations of robot apps. We introduce security policies for each type of risks, and design coordination nodes to enforce the policies and regulate the interactions. We conduct extensive experiments on 110 robot apps from the ROS platform and two complex apps (Baidu Apollo and Autoware) widely adopted in industry. Evaluation results indicated RTron can correctly identify and mitigate all potential risks with negligible performance cost. To validate the practicality of the risks and solutions, we implement and evaluate RTron on a physical UGV (Turtlebot) with real-word apps and environments. © 2021 ACM.

关键词： Risk analysis

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