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30th Great Lakes Symposium on VLSI, GLSVLSI 2020

作者： Fu, Rongliang Zhang, Zhi-Min Tang, Guang-Ming Huang, Junying Ye, Xiao-Chun Fan, Dong-Rui Sun, Ning-Hui State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China School of Computer Science and Technology University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450379441

The superconducting rapid single flux quantum (RSFQ) logic circuit has the characteristics of high speed and low power consumption, making it an attractive candidate for future supercomputers. However, computer-aided design (CAD) tools for CMOS cannot be directly applied to RSFQ logic due to their distinct properties. For instance, the RSFQ logic gate can work properly when all its fan-ins have the same logic level. This paper presents the design flow from RTL to RSFQ logic netlist and schematic. First, we implement logic synthesis for RSFQ logic circuits. It achieves path balancing while minimizing the number of DFFs. In addition, we propose an automatic schematic generator for the RSFQ logic circuits. It converts the synthesized netlist into its equivalent schematic. A layer assignment algorithm is proposed, which makes all gates layered in the order of the clock arrival time. Experimental results with ISCAS85 and EPFL benchmarks along with some Kogge-Stone adders have shown a 29.2% reduction in the number of DFFs over the breadth-first first search;moreover, 59.57% and 5.3% decrease in the number of layers of the schematic and number of edge crossings over the ELK tool. © 2020 Association for Computing Machinery.

关键词： Logic circuits

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Isolation Forest Based Interest Flooding Attack Detection Mechanism in NDN 2

Isolation Forest Based Interest Flooding Attack Detection Me...

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2nd IEEE International Conference on Hot Information-Centric Networking, HotICN 2019

作者： Chen, Jing Xing, Guanglin Cui, Mengtian Huo, Hong Hou, Rui College of Computer Science South-Central University for Nationalities Wuhan China Key Laboratory of Computer System State Ethnic Affairs Commission Southwest Minzu University Chengdu China

ISBN: (纸本)9781728157818

Interest flooding attack (IFA) can considerably harm named data networking (NDN). To prevent an IFA, in this paper, we propose an isolation forest (iForest) based IFA detection mechanism and provide a countermeasure. In this mechanism, the iForest is constructed based on the prefixes of interest packets, where the abnormal prefixes are isolated closer to the root node, and the normal prefixes are isolated farther from the root node. Furthermore, we detect malicious prefixes from abnormal prefixes according to the usage of pending interest table (PIT);thus, the forwarding of interest packets with malicious prefixes is restricted, and the influences of IFA are reduced. Simulation results show that the proposed mechanism can effectively increase the number of data packets received by consumers, thus mitigating IFA. © 2019 IEEE.

关键词： Forestry

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DLPlib： A Library for Deep Learning Processor

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Journal of computer Science & Technology 2017年第2期32卷 286-296页

作者： Hui-Ying Lan Lin-Yang Wu Xiao Zhang Jin-Hua Tao Xun-Yu Chen Bing-Rui Wang Yu-Qing Wang Qi Guo Yun-Ji Chen State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Microprocessor Research Center Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China Department of Computer Science University of Science and Technology of China Hefei 230026 China

Recently, deep learning processors have become one of the most promising solutions of accelerating deep learning algorithms. Currently, the only method of programming the deep learning processors is through writing assembly instructions by bare hands, which costs a lot of programming efforts and causes very low efficiency. One solution is to integrate the deep learning processors as a new back-end into one prevalent high-level deep learning framework （e.g., TPU （tensor processing unit） is integrated into Tensorflow directly）. However, this will obstruct other frameworks to profit from the programming interface, The alternative approach is to design a framework-independent low-level library for deep learning processors （e.g., the deep learning library for GPU, cuDNN）. In this fashion, the library could be conveniently invoked in high-level programming frameworks and provides more generality. In order to allow more deep learning frameworks to gain benefits from this environment, we envision it as a low-level library which could be easily embedded into current high-level frameworks and provide high performance. Three major issues of designing such a library are discussed. The first one is the design of data structures. Data structures should be as few as possible while being able to support all possible operations. This will allow us to optimize the data structures easier without compromising the generality. The second one is the selection of operations, which should provide a rather wide range of operations to support various types of networks with high efficiency. The third is the design of the API, which should provide a flexible and user-friendly programming model and should be easy to be embedded into existing deep learning frameworks. Considering all the above issues, we propose DLPIib, a tensor-filter based library designed specific for deep learning processors. It contains two major data structures, tensor and filter, and a set of operators including basic neur

关键词： deep learning processor API library DLPlib

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HDCat: Effectively identifying hot data in large-Scale I/O streams with enhanced temporal locality 15th

HDCat: Effectively identifying hot data in large-Scale I/O s...

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15th International Conference on Algorithms and architectures for Parallel Processing, ICA3PP 2015

作者： Chen, Jiahao Deng, Yuhui Huang, Zhan Department of Computer Science Jinan University Guangzhou510632 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100190 China

ISBN: (纸本)9783319271217

Hot data is very important for optimizing modern computer systems. For example, the identified hot data can be employed to extend the lifespan of flash memory. However, it is very challenging to effectively identify hot data with low memory consumption and low runtime overhead. This paper proposes a Hot Data Catcher (HDCat) which can effectively identify hot data in large-scale I/O streams by leveraging enhanced temporal locality. HDCat only maintains a hot data queue and a candidate hot data queue to record the data access pattern by tracking limited data set, thus effectively reducing the memory consumption. Furthermore, HDCat adopts a D-bit counter and a recency-bit to leverage both the frequency and recency contained in the data stream. Additionally, HDCat can significantly reduce the conversion between hot data and cold data. Real traces are used to evaluate the proposed approach. Experimental results demonstrate that HDCat significantly outperforms the state-of-the-art Multi-hash algorithm and the two-level LRU algorithm. © Springer International Publishing Switzerland 2015.

关键词： Hash functions

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Designing a power-aware replication strategy for storage clusters

Designing a power-aware replication strategy for storage clu...

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2013 IEEE International Conference on Green Computing and Communications and IEEE Internet of Things and IEEE Cyber, Physical and Social Computing, GreenCom-iThings-CPSCom 2013

作者： Zhang, Lingwei Deng, Yuhui Department of Computer Science Jinan University Guangzhou 510632 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

ISBN: (纸本)9780769550466

The exponential data growth is presenting challenges to traditional storage systems. Component-based cluster storage systems, due to their high scalability, are becoming the architecture of next generation storage systems. Cluster storage systems often use data replication to ensure high availability, fault tolerance, and load balance. However, this kind of data replication not only consumes a large amount of storage resources, but also generates more energy consumption. This paper presents a power-aware data replication strategy by leveraging data access behavior. This strategy uses 80/20 rule (80% of the data accesses often go to 20% of the storage space) to replicate only a small amount of frequently accessed data. Furthermore, the storage nodes are divided into a hot node set and a cold node set. Hot nodes, which store a small amount of hot data copies, are always in an active state to guarantee the QoS of the system. The cold nodes which store a large number of infrequently accessed cold data, are placed in a low power state, thus reducing the energy consumption of the cluster storage system. The experimental results show that the proposed strategy can effectively reduce the resource and energy consumption of the system, while ensuring the system performance. © 2013 IEEE.

关键词： Energy utilization

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Robust temporal alignment for multivariate time series forecasting

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Expert systems with Applications 2025年 289卷

作者： Xuguang Wang Mi Zhang Jie Su School of Control and Computer Engineering North China Electric Power University 619 Yonghuabei Street Lianchi District Baoding 071003 PR China Baoding Key Laboratory of State Detection and Optimization Regulation for Integrated Energy System 619 Yonghuabei Street Lianchi District Baoding 071003 PR China

Temporal alignment of time series is crucial in the task of multivariate time series forecasting, as temporal misalignment can introduce randomness into the learned quantitative relationships between the target and related factor time series, resulting in unreliable forecasting outcomes. Nevertheless, anomalous information gain (AIG) and data outliers present significant challenges to the temporal alignment of time series. To address the issues of AIG and data outliers in this study, a time-delay-related ellipsoid is utilized to construct the alignment deviation metric, an information gain-based regularization term is designed to reinforce this metric by penalizing the occurrence of AIG, and an equiprobable ellipsoid-based outlier filtering process is introduced. Finally, a time-delay estimation (TDE) method robust to AIG and data outliers is proposed, upon which the time series alignment is performed. The robustness of the proposed method against AIG and data outliers is validated through simulation and real-data experiments. The wind speed forecast errors of the forecasting models are significantly reduced after aligning the related time series using our method; for instance, the mean squared error (MSE) achieved by traditional machine learning models and deep learning models is reduced to at least 74 % and 95 %, respectively.

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Poster: Revisiting virtual channel memory for performance and fairness on multi-core architecture 11

Poster: Revisiting virtual channel memory for performance an...

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Proceedings of the international conference on Supercomputing

作者： Chen, Licheng Huang, Yongbing Bao, Yungang Mutlu, Onur Tan, Guangming Chen, Mingyu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate School of Chinese Academy of Sciences China Carnegie Mellon University United States

ISBN: (纸本)9781450301022

In modern multi-core chip architecture, the DRAM system is shared by more and more cores and high bandwidth I/O devices. This trend would make the problem of request contention and un-fairness more serious. Previous research focused on memory sche-duling mechanisms to efficiently and fairly serve memory requests generated by multiple cores. However, the performance is mod-erately improved due to the limited bank-level parallelism in preva-lent DRAM chips. Based on the observation that virtual channel memory (VCM) provides more opportunities for exploiting MLP because it has more channel buffers than banks in conventional DRAM chip, we evaluate VCM technology as an alternative to DRAM for addressing the issues of contention, unfairness and MLP. In this work we implement VCM and leverage the state of art scheduling mechanism on a multi-core architecture. The experi-mental results show that (i) VCM with 32 channels improves ho-mogeneous workloads' IPC by 2.08X on a 16-core system compared to the system with conventional DRAM chips, causing extra area cost by 0.5%, and dynamic and background power pe-nalties by only 5.8% and 0.03% respectively. (ii) For heterogene-ous workloads, VCM significantly reduces unfairness by 82.0% as well as improves the workloads' performance by 1.86X in term of system throughput. © 2011 Authors.

关键词： Dynamic random access storage

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Test cost efficiency exploration for CMT processors

Test cost efficiency exploration for CMT processors

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IEEE Region 10 International Conference TENCON

作者： Jia Li Yu Hu Xiaowei Li Key Laboratory of Computer System and Architecture ICT CAS Beijing China

Chip multi-threading (CMT) is an architecture that can achieve overall high performance by exploiting high bandwidth rather than high frequency, thus reduce hardware complexity and power. Test cost of this architecture also can be reduced by efficiently utilizing its communication channel bandwidth during test. Because CMT architectures are designed low-power in nature, its testing should also be conducted under stringent power constraints. This paper discusses these above problems and proposes a cost-efficient test scheme. Experimental results show that our test scheme can achieve very short test time and low test data volume under stringent power constraints with low area overhead.

关键词： Costs Bandwidth system testing computer architecture Frequency Hardware Thermal management Power dissipation Network-on-a-chip Laboratories

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The implementation and design methodology of a quad-core version Godson-3 microprocessor

The implementation and design methodology of a quad-core ver...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： Baoxia Fan Liang Yang Zhuo Gao Feng Zhang Ru Wang Key Laboratory of Computer System and Architecture ICT CAS Beijing China

Godson-3A is a quad-core version of Godson-3 series which is a 174 mm 2 , 425 million transistors chip fabricated using 65 nm CMOS LP/GP process technology. It can be running at 1 GHz with less than 15 W power consumption. Large scale, high frequency, low power and tight time schedule make great challenges in the chip design. To overcome these challenges, a design methodology based on ASIC combining with semi-custom (manual placement and routing using standard cells) and full-custom is adopted. This paper describes the implementation of Godson-3A microprocessor and the methodology used in the chip design.

关键词： Design methodology Microprocessors Chip scale packaging CMOS process CMOS technology Energy consumption Large-scale systems Frequency Processor scheduling Application specific integrated circuits

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Energy-Efficient Input Buffer Design using Data-Transition Oriented Model

Energy-Efficient Input Buffer Design using Data-Transition O...

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International Symposium on Integrated Circuits (ISIC)

作者： Jun Wang Kun Huang Ge Zhang Weiwu Hu Feng Zhang Key Laboratory of Computer System and Architecture ICT CAS Beijing China

Network-on-chip (NoC) has been proved to be an efficient solution for interconnection between processor cores in chip multi-processor (CMP), which will consume extra energy. This paper is focusing on the energy-efficient design of input buffer, one of the most critical components in NoC. For precise calculation of energy, data-transition oriented model with multilevel simulations is proposed here. And using our method, a suit of benchmarks, SPLASH-2, are executed to evaluate the designs with different physical parameters and circuit structures. The simulations are based on 90 nm CMOS process, and the input buffer with 64-bit width and 16-entry depth is recommended for more energy-efficiency.

关键词： Energy efficiency Network-on-a-chip Energy consumption Circuit simulation Integrated circuit interconnections Bandwidth Laboratories computer networks computer architecture Content addressable storage

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