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International Conference on Software Maintenance (ICSM)

作者： Jingtang Zhang Kui Liu Dongsun Kim Li Li Zhe Liu Jacques Klein Tegawendé F. Bissyandé Nanjing University of Aeronautics and Astronautics Nanjing China Key Laboratory of Safety-Critical Software (Nanjing University of Aeronautics and Astronautics) Nanjing China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi China Kyungpook National University Daegu South Korea Monash University Melbourne Australia Interdisciplinary Centre for Security Reliability and Trust (SnT) University of Luxembourg Luxembourg

Fault localization produces bug positions as the basic input for many automated program repair (APR) systems. Given that test cases are the common means that automatic fault localization techniques leverage, we investigate the impact of their characteristics (in terms of quality and quantity) on APR. In particular, we analyze the statements that appear in crash stack traces when test cases fail (note that stack traces are available when an ordinary test case fails since its verdict is often made by assertions that produce errors such as AssertError in Java and JUnit), and explore the possibility of using some relevant crash information to enhance fault localization; this ultimately improves the effectiveness of APR tools. Our study reveals that the considered state-of-the-art APR systems achieve the best performance when fixing bugs associated with boolean type expected values (e.g., assertTrue ()) or assertFalse(). In contrast, they achieve their worst performance when addressing bugs related to null check assertions. Meanwhile, null check bugs as well as the bugs associated with boolean and string type expected values are still the main challenge that should be addressed by the future APR. For exception throwing bugs, existing APR systems present the best performance on fixing NullPointerException bugs, while the tough task of them is to resolve the bugs throwing developer-defined exceptions. The information in stack traces after executing the bug-triggering test cases can be used to effectively improve the performance on fault localization and program repair.

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A biologically plausible audio-visual integration model for continual learning

arXiv

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arXiv 2020年

作者： Chen, Wenjie Du, Fengtong Wang, Ye Cao, Lihong State Key Laboratory of Media Convergence and Communication Communication University of China Beijing China Neuroscience and Intelligent Media Institute Communication University of China Beijing China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi China

The problem of catastrophic forgetting has a history of more than 30 years and has not been completely solved yet. Since the human brain has natural ability to perform continual lifelong learning, learning from the brain may provide solutions to this problem. In this paper, we propose a novel biologically plausible audio-visual integration model (AVIM) based on the assumption that the integration of audio and visual perceptual information in the medial temporal lobe during learning is crucial to form concepts and make continual learning possible. Specifically, we use multi-compartment Hodgkin-Huxley neurons to build the model and adopt the calcium-based synaptic tagging and capture as the model’s learning rule. Furthermore, we define a new continual learning paradigm to simulate the possible continual learning process in the human brain. We then test our model under this new paradigm. Our experimental results show that the proposed AVIM can achieve state-of-the-art continual learning performance compared with other advanced methods such as OWM, iCaRL and GEM. Moreover, it can generate stable representations of objects during learning. These results support our assumption that concept formation is essential for continuous lifelong learning and suggest the proposed AVIM is a possible concept formation mechanism. Copyright © 2020, The Authors. All rights reserved.

关键词： Brain

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A Large-Scale Study of Failures on Petascale Supercomputers

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Journal of Computer Science & Technology 2018年第1期33卷 24-41页

作者： Rui-Tao Liu Zuo-Ning Chen State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi 213215 China National Research Center of Parallel Computer Engineering and Technology Beijing 100190 China

With the rapid development of supercomputers, the scale and complexity are ever increasing, and the reliability and resilience are faced with larger challenges. There are many important technologies in fault tolerance, such as proacrive failure avoidance technologies based on fault prediction, reactive fault tolerance based on checkpoint, and scheduling technologies to improve reliability. Both qualitative and quantitative descriptions on characteristics of system faults are very critical for these technologies, This study analyzes the source of failures on two typical petascale supercomputers called Sunway BlueLight （based on multi-core CPUs） and Sunway TaihuLight （based on heterogeneous manycore CPUs）. It uncovers some interesting fault characteristics and finds unknown correlation relationship among main components＇ faults. Finally the paper analyzes the failure time of the two supercomputers in various grains of resource and different time spans, and builds a uniform multi-dimensional failure time model for petascale supereomputers.

关键词： petascale supercomputer fault characteristic correlation relationship multi-dimension failure time model

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BTI Aging Monitoring based on SRAM Start-up Behavior

BTI Aging Monitoring based on SRAM Start-up Behavior

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Asian Test Symposium (ATS)

作者： Shengyu Duan Peng Wang Gaole Sai School of Computer Engineering and Science Shanghai University Shanghai China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi China Guangdong Provincial Key Lab of Robotics and Intelligent System Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences China CAS Key Laboratory of Human-Machine Intelligence-Synergy Systems Shenzhen Institutes of Advanced Technology China

ISBN: (数字)9781728174679

ISBN: (纸本)9781728174686

Bias Temperature Instability (BTI) is one of the dominant CMOS aging mechanisms. It causes time-dependent variation, threatening circuit lifetime reliability. BTI-induced circuit errors are not detectable at the fabrication stage. On-line monitoring schemes are therefore necessary to capture the degradations during the operational time. Traditional aging monitoring techniques exhibit high implementation complexity and low stability. In this paper, we propose a BTI monitoring approach by simply tracking the start-up behavior of SRAM cells. SRAM is a widely used on-chip device in many applications. We study the impact of BTI for SRAM start-up values and age some cells in a manipulated manner. The BTI degradation is evaluated based on the number of SRAM cells starting with a certain value. This technique can be used to estimate the degradation for on-chip logic circuits without introducing additional circuitry, and thus has very low implementation complexity. We use an SRAM array with 1024 cells to estimate the degradations for multiple logic circuits, and show the average mean absolute percentage error as 8.48%. In addition, this technique is robust considering process, voltage and temperature variations.

关键词： Degradation Monitoring Logic circuits Transistors SRAM cells Aging System-on-chip

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Terahertz Generation via Picosecond Spin-to-Charge Conversion in IrMn3/Ni−Fe Heterojunction

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Physical Review Applied 2021年第2期16卷 024058-024058页

作者： Cheng Li Bin Fang Like Zhang Qian Chen Xiangnan Xie Nuo Xu Zhongming Zeng Zhenyu Wang Liang Fang Tian Jiang Institute for Quantum Information & State Key Laboratory of High Performance Computing National University of Defense Technology Changsha 410073 China Physical Science and Engineering Division King Abdullah University of Science and Technology Thuwal 23955-6900 Saudi Arabia Suzhou Institute of Nano-Tech and Nano-Bionics CAS Suzhou 215123 China College of Electronic and Information Engineering Wuxi University Wuxi 214105 China National Innovation Institute of Defense Technology Academy of Military Sciences PLA China Beijing 100010 China Beijing Academy of Quantum Information Sciences Beijing 100193 China Beijing Institute for Advanced Studies National University of Defense Technology 100010 China

Experimental investigations of ultrafast electro-optical properties in magnetic materials manifest their great potential for emerging spintronic optoelectronic devices. Here, using time-resolved terahertz emission spectroscopy, we construct a spintronic terahertz emitter consisting of an IrMn3/Ni−Fe heterojunction. A femtosecond spin current pulse is generated in the thin film of the Ni−Fe layer when it absorbs a femtosecond laser pulse, and then the spin current is converted into a transient charge current by the metallic IrMn3 layer on picosecond timescales. We timely record the terahertz emission associated with this ultrafast conversion process by means of electro-optic sampling. Besides, the spin-to-charge conversion efficiency of the IrMn3/Ni−Fe heterojunction is determined via quantitative analysis of the spin torque ferromagnetic resonance results. We have both optically verified and electrically studied the spin-to-charge conversion of the IrMn3/Ni−Fe heterojunction. Our results enlarge the material choice range of spintronic terahertz emitters, which may promote further investigations of ultrafast spin-to-charge conversion in different heterojunction materials.

关键词： Magnetization dynamics Optical sources & detectors Optoelectronics Spin current Spin-orbit coupling Ultrafast magnetic effects Magnetic multilayers Terahertz techniques

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Network representation learning: From preprocessing, feature extraction to node embedding

arXiv

引用

arXiv 2021年

作者： Zhou, Jingya Liu, Ling Wei, Wenqi Fan, Jianxi Soochow University 1 Shizi street Jiangsu Suzhou215006 China Georgia Institute of Technology during May 2019 - June 2020 AtlantaGA United States State Key Laboratory of Mathematical Engineering and Advanced Computing Jiangsu Wuxi214125 China Georgia Institute of Technology 801 Atlantic Drive AtlantaGA30332 United States Soochow University 1 Shizi street Jiangsu Suzhou215006 China

Network representation learning (NRL) advances the conventional graph mining of social networks, knowledge graphs, and complex biomedical and physics information networks. Over dozens of network representation learning algorithms have been reported in the literature. Most of them focus on learning node embeddings for homogeneous networks, but they differ in the specific encoding schemes and specific types of node semantics captured and used for learning node embedding. This survey paper reviews the design principles and the different node embedding techniques for network representation learning over homogeneous networks. To facilitate the comparison of different node embedding algorithms, we introduce a unified reference framework to divide and generalize the node embedding learning process on a given network into preprocessing steps, node feature extraction steps and node embedding model training for a NRL task such as link prediction and node clustering. With this unifying reference framework, we highlight the representative methods, models, and techniques used at different stages of the node embedding model learning process. This survey not only helps researchers and practitioners to gain an in-depth understanding of different network representation learning techniques but also provides practical guidelines for designing and developing the next generation of network representation learning algorithms and systems. © 2021, CC BY.

关键词： Feature extraction

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A Non-Stop Double Buffering Mechanism for Dataflow Architecture

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Journal of Computer Science & Technology 2018年第1期33卷 145-157页

作者： Xu Tan Xiao-Wei Shen Xiao-Chun Ye Da Wang Dong-Rui Fan Lunkai Zhang Wen-Ming Li Zhi-Min Zhang Zhi-Min Tang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing 100049 China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi 214125 China Department of Computer Science The University of Chicago Chicago IL 60637 U.S.A.

Double buffering is an effective mechanism to hide the latency of data transfers between on-chip and off-chip memory. However, in dataflow architecture, the swapping of two buffers during the execution of many tiles decreases the performance because of repetitive filling and draining of the dataflow accelerator. In this work, we propose a non-stop double buffering mechanism for dataflow architecture. The proposed non-stop mechanism assigns tiles to the processing element array without stopping the execution of processing elements through optimizing control logic in dataflow architecture. Moreover, we propose a work-flow program to cooperate with the non-stop double buffering mechanism. After optimizations both on control logic and on work-flow program, the filling and draining of the array needs to be done only once across the execution of all tiles belonging to the same dataflow graph. Experimental results show that the proposed double buffering mechanism for dataftow architecture achieves a 16.2% average efficiency improvement over that without the optimization.

关键词： non-stop double buffering dataflow architecture high-performance computing

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A Pipelining Loop Optimization Method for Dataflow Architecture

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Journal of Computer Science & Technology 2018年第1期33卷 116-130页

作者： Xu Tan Xiao-Chun Ye Xiao-Wei Shen Yuan-Chao Xu Da Wang Lunkai Zhang Wen-Ming Li Dong-Rui Fan Zhi-Min Tang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing 1000J9 China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi 214125 China College of Information Engineering Capital Normal University Beijing 100048 China Department of Computer Science The University of Chicago Chicago IL 60637 U.S.A.

With the coming of exascale supercomputing era, power efficiency has become the most important obstacle to build an exascale system. Dataflow architecture has native advantage in achieving high power efficiency for scientific applications. However, the state-of-the-art dataflow architectures fail to exploit high parallelism for loop processing. To address this issue, we propose a pipelining loop optimization method （PLO）, which makes iterations in loops flow in the processing element （PE） array of dataflow accelerator. This method consists of two techniques, architecture-assisted hardware iteration and instruction-assisted software iteration. In hardware iteration execution model, an on-chip loop controller is designed to generate loop indexes, reducing the complexity of computing kernel and laying a good f（mndation for pipelining execution. In software iteration execution model, additional loop instructions are presented to solve the iteration dependency problem. Via these two techniques, the average number of instructions ready to execute per cycle is increased to keep floating-point unit busy. Simulation results show that our proposed method outperforms static and dynamic loop execution model in floating-point efficiency by 2.45x and 1.1x on average, respectively, while the hardware cost of these two techniques is acceptable.

关键词： dataflow model control-flow model loop optimization exascale computing scientific application

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Factorization of odd integers as lattice search procedure 1

引用

9th International Symposium on Intelligence Computation and Applications, ISICA 2017

作者： Wang, Xingbo Foshan University Foshan CityGuangdong Province528000 China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi China

ISBN: (数字)9789811316517

ISBN: (纸本)9789811316500

The article puts forward a 3-dimensional searching approach that can factorize odd composite integers. The article first proves that, an odd composite number can be expressed by a trivariate function, then demonstrates that factorization of an odd integer can be turned into a problem of searching a point in a 3-dimensional cube whose points can be searched rapidly via octree search algorithm or other 3-dimensional searching algorithm. Mathematical principles with their proofs are presented in detail, and an algorithm that reaches square of logarithm time-complexity is proposed with numerical examples. The proposed algorithm can be applied both in sequential computation and parallel computation. © 2018, Springer Nature Singapore Pte Ltd.

关键词： Factorization

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Intra-pulse Intentional Modulation Recognition of Radar Signals at Low SNR 2

Intra-pulse Intentional Modulation Recognition of Radar Sign...

引用

2nd IEEE International Conference on Circuits, System and Simulation, ICCSS 2018

作者： Xi, Tian Yishan, Liu Xianyue, Pan Wentao, Chen College of Electronic Science and Engineering National University of Defense Technology Changsha China State Key Laboratory of Mathemsatical Engineering and Advanced Computing Wuxi China

ISBN: (纸本)9781538678190

Intra-pulse features extraction of radar is of great research significance in electronic reconnaissance technology. With continuous development and equipment of the new system radar, the characteristics of the modern electromagnetic environment could be summarized as density, complexity and variability, which make the traditional signal identification methods difficult to achieve the desired effect. Therefore, this paper is devoted to the study the methods and performance analysis in extracting intra-pulse features of radar emitters in complex electromagnetic environment, especially in low SNR environment. The final recognition effect exceeded 0db SNR. © 2018 IEEE.

关键词： Singular value decomposition

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