The sentiment mining is a fast growing topic of both academic research and commercial applications, especially with the widespread of short-text applications on the Web. A fundamental problem that confronts sentiment ...
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ISBN:
(纸本)9781479967162
The sentiment mining is a fast growing topic of both academic research and commercial applications, especially with the widespread of short-text applications on the Web. A fundamental problem that confronts sentiment mining is the automatics and correctness of mined sentiment. This paper proposes an DLDA (Double Latent Dirichlet Allocation) model to analyze sentiment for short-texts based on topic model. Central to DLDA is to add sentiment to topic model and consider sentiment as equal to topic, but independent of topic. DLDA is actually two methods DLDA I and its improvement DLDA II. Compared to the single topic-word LDA, the double LDA I, i.e., DLDA I designs another sentiment-word LDA. Both LDAs are independent of each other, but they combine to influence the selected words in short-texts. DLDA II is an improvement of DLDA I. It employs entropy formula to assign weights of words in the Gibbs sampling based on the ideas that words with stronger sentiment orientation should be assigned with higher weights. Experiments show that compared with other traditional topic methods, both DLDA I and II can achieve higher accuracy with less manual needs.
Most processors employ hardware data prefetching to hide memory access latencies. However the prefetching requests from different threads on a multi-core processor can cause severe interference with prefetching and/or...
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ISBN:
(纸本)9781479964932
Most processors employ hardware data prefetching to hide memory access latencies. However the prefetching requests from different threads on a multi-core processor can cause severe interference with prefetching and/or demand requests of others. The data prefetching can lead to significant performance degradation due to shared resource contention on shared memory multi-core systems. This paper proposes a thread-aware data prefetching mechanism based on low-overhead run-time information to tune prefetching modes and aggressiveness, mitigating the resource contention in the memory system. Our solution has two new components: 1) a filtering mechanism that informs the hardware about which prefetching requests can cause shared data invalidation and should be discarded, and 2) a self-tuning prefetcher that uses run-time feedback to adjust each thread's data prefetching mode and arguments. On a set of parallel benchmarks, our thread-aware data prefetching mechanisms improve the overall performance of 64-core system by 11% and reduce the energy-delay product by 13% over a multi-mode prefetch baseline system with a two level cache organization and a conventional MESI-based directory coherence protocol. We compare our approach to the feedback directed prefetching (FDP) technique and find that it provides better performance on multi-core systems, while reducing the energy delay product.
The typical features of graph algorithm represented by breadth-first search (BFS) were investigated, and a lightweight heuristic switch strategy was designed and implemented by automatically switching through two basi...
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Integrating a large number of simple cores on the chip to provide the desired performance and throughput, microprocessor has entered the many core era. In order to fully extract the ability of the many core processor,...
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ISBN:
(纸本)9781479952465
Integrating a large number of simple cores on the chip to provide the desired performance and throughput, microprocessor has entered the many core era. In order to fully extract the ability of the many core processor, we propose speedup models for many core architecture in this paper. Under the assumption of Hill-Marty model, we deduce our formulas based on Gustafson's Law and Sun-Ni's Law. Then, compared with the Hill-Marty model, we theoretically analyze the best allocation under the given resources. Furthermore, we apply the conclusions of our models to evaluate current many core processors and predict concrete future architecture. Our results show that the many core architecture is capable of extensive scalability and being beneficial to promote the performance, especially heterogeneous one. By using simple analytical models, we provide a better understanding of architecture design and our work complement existing studies.
Modular multiplication is one of the most important operations in the public key cryptographic algorithms. In order to design a high-performance modular multiplier, we present a novel hybrid Montgomery modular multipl...
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Modular multiplication is one of the most important operations in the public key cryptographic algorithms. In order to design a high-performance modular multiplier, we present a novel hybrid Montgomery modular multiplier over GF(p) on FPGAs, which employs Karatsuba and Knuth multiplication algorithms in different levels to implement large integer multiplication. A 9-stage pipeline full-word multiplier is proposed for the 256-bit multiplication with 4-level recursion. The performance of our modular multiplier is improved through optimizing the pipeline and reducing carry-chain latency of the modular adder. On average, our modular multiplier can perform one 256-bit modular multiplication in 3 cycles. We can integrate 13 modular multipliers on a Xilinx Virtex-6 V6VSX475T FPGA. The experimental results show that the throughput of 856.9 million modular multiplications per second can be achieved and the hybrid Montgomery modular multiplier has an outstanding performance in the situations which need continuous multiplications.
There are two main approaches to achieve selective opening chosen-cipher text security (SO-CCA security): lossy encryption (including all-but-many lossy trapdoor functions) and sender-equivocable encryption. The secon...
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