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Compact millimeter-wave air-filled substrate-integrated waveguide crossover employing homogeneous cylindrical lens

Frontiers of Information technology & Electronic Engineering 2023年第9期24卷 1366-1374页

作者： Chun GENG Jiwei LIAN Dazhi DING Qian Xuesen College Nanjing University of Science and TechnologyNanjing 210094China School of Microelectronics(School of Integrated Circuits) Nanjing University of Science and TechnologyNanjing 210094China State Key Laboratory of Millimeter Waves Southeast UniversityNanjing 210096China

We propose a new method to design crossovers by employing an embedded homogeneous cylindrical lens(HCL).Compared with traditional crossover designs,this strategy introduces an HCL within the air-filled substrate-integrated waveguide(SIW)crossover cavity to direct the incident waves in the desired *** to ray-tracing analysis,the added HCL can efficiently concentrate the electromagnetic wave propagating from the input to the output without increasing the fabrication complexity or footprint.

关键词： waveguide millimeter crossover

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High Short-Circuit Capability and Low-Loss SOI-LIGBT with Double-integrated NMOS

High Short-Circuit Capability and Low-Loss SOI-LIGBT with Do...

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International Conference on Solid-state and integrated Circuit technology

作者： Jialei Tan Jie Wei Jinlong Lu Xindi Liu Gaoqiang Deng Wei Song Pei Guo Bo Zhang Xiaorong Luo State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology of China Chengdu China College of Microelectronics Chengdu University of Information Technology Chengdu China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

A novel SOI lateral insulated gate bipolar transistor (LIGBT) featuring double-integrated NMOS (DNM) is proposed and investigated. The DNM (MOS1 and MOS2) self-adaptively controls the states of parasitic diode $\mathrm{D}_0$ (P-well/N+ cathode). In the on state, the Do adaptively turns on to enhance the conductivity modulation effect to improve the on-state voltage drop $(V_{\mathrm{o}\mathrm{n}})$ . In the saturation and short circuit state with high anode voltage $(V_\text{AK})$ , the $\mathrm{D}_0$ is adaptively turned off and reverse-biased to reduce the saturation current $(I_{\mathrm{s}\mathrm{a}\mathrm{t}})$ and improve the latch-up immunity and achieve a better short-circuit withstanding time $(t_{\mathrm{s}\mathrm{c}})$ . During turning-off period with increasing $V_{\text{AK}}$ , the DNM LIGBT significantly reduces turnoff loss $(E_{\text{off}})$ due to the adaptively turn-on MOS1 providing a low resistance path to extract the stored carriers quickly. DNM LIGBT decreases the $E_{\text{off}}$ by 76% at the same $V_{\text{on}}$ compared with the SCM LIGBT and improves $t_{\mathrm{s}\mathrm{c}}$ by 252% and 27% compared with those of Con. and SCM LIGBTs.

关键词： Resistance integrated circuit technology Insulated gate bipolar transistors Modulation Voltage Conductivity Turning Sulfur Molybdenum MOS devices

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Novel Heterojunction Field Plate $\beta-\text{Ga}_{2}\mathrm{O}_{3}$ MOSFET with High Breakdown Voltage

Novel Heterojunction Field Plate $\beta-\text{Ga}_{2}\mathrm...

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International Conference on Solid-state and integrated Circuit technology

作者： Xiangnan Li Jie Wei Kai Zhao Linyao Hao Xiaosong Peng Yuxi Wei Renkuan Liu Wei Song Pei Guo Xiaorong Luo State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology of China Chengdu China College of Microelectronics Chengdu University of Information Technology Chengdu China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

A novel $\beta-\text{Ga}_{2}\mathrm{O}_{3}$ metal-oxide-semiconductor field-effect transistor (MOSFET) featured heterojunction field plate (HFP) is proposed to enhance its breakdown voltage $(BV)$ and reduce specific ON-resistance $(R_{\text{ON,SP}})$ , and its mechanism is investigated by simulation. The HFP is composed of P-NiO above the drift and regrown $\text{Ga}_{2}\mathrm{O}_{3}$ at drain side. The P-NiO and N-drift $\text{Ga}_{2}\mathrm{O}_{3}$ work like the P/N pillars of superjunction. Thus, the HFP structure not only modulates the surface electric field (E-field) distribution to improve the $BV$ in the off-state, but also introduces assisted depletion effect to improve the drift doping concentration to reduce the $R_{\text{ON,SP}}$ . Based on the charge balance principle between the P-NiO and N-drift $\text{Ga}_{2}\mathrm{O}_{3}$ , the $BV$ , power-figure-of-merit $\left(\text{PFOM}=B V^2 / \text{Ron}, \text{SP}\right)$ and $R_{\text{ON},\text{SP}}$ of the proposed HFP $\beta-\text{Ga}_{2}\mathrm{O}_{3}$ MOSFET are improved by 40.5%, 230.8% and 40.3% compared with those of conventional $\beta-\text{Ga}_{2}\mathrm{O}_{3}$ MOSFET at the same dimensions. Thus, this proposed device provides a new design strategy for high-power $\beta-\text{Ga}_{2}\mathrm{O}_{3}$ MOSFETs.

关键词： integrated circuit technology MOSFET High-voltage techniques Doping Heterojunctions Transistors Electric fields

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Impact of Proton Radiation on Zr-Doped HfO2-Based Ferroelectric Memory

SSRN

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SSRN 2024年

作者： Zhu, Xuhao Ma, Yao Bi, Jinshun Xu, Gaobo He, Mu Mei, Fan Yuan, Yihui Li, Shirui Wang, Yulin Zou, Peichun Zhao, Xue Key Laboratory of Microelectronics College of Physics Sichuan University Chengdu610064 China School of Integrated Circuits Key Laboratory of Microelectronics College of Physics Sichuan University Chengdu610064 China School of Integrated Circuits University of Chinese Academy of Sciences Beijing100049 China State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of Chinese Academy of Sciences Beijing100029 China Sichuan Xu Mao Micro Technology Co.Ltd China

HfO2-based ferroelectric random access memory (FeRAM) has attracted tremendous attention in the field of data storage. However, the radiation performance and tolerance of FeRAM have not been investigated comprehensively. In this work, the electrical and structural properties of the W/TiN/Zr-doped HfO2(HZO)/TiN ferroelectric memory after radiation by 5 MeV proton at room temperature (RT) and low temperature (LT) were studied. After performing electrical and piezoresponse force microscopy (PFM) characterization, it was demonstrated that the radiation effect of HZO MFM ferroelectric memory strongly depends on the radiation temperature. The dielectric constant (Εr) and the remanent polarization (2Pr) values of the capacitor first decreased and then increased with the increasing of fluence at RT. Once the HZO thin film was radiated by protons at extremely low temperature, the performance of the HZO memory would be completely degraded. The increased ferroelectric properties due to RT radiation will be partially weakened after annealing at room temperature. The ferroelectric properties of the samples radiated by LT proton radiation would be restored due to the domain unpinning effect. © 2024, The Authors. All rights reserved.

关键词： Ferroelectricity

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tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling

tSS-BO: Scalable Bayesian Optimization for Analog Circuit Si...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Tianchen Gu Jiaqi Wang Zhaori Bi Changhao Yan Fan Yang Yajie Qin Tao Cui Xuan Zeng State Key Laboratory of Integrated Chips and Systems School of Microelectronics Fudan University Shanghai China State Key Laboratory of Scientific and Engineering Computing Academy of Mathematics and Systems Science Chinese Academy of Sciences & University of Chinese Academy of Sciences Beijing China State Key Laboratory of Integrated Chips and Systems School of Information Science and Technology Fudan University Shanghai China

ISBN: (数字)9783981926385

ISBN: (纸本)9798350348606

We propose a novel scalable Bayesian optimization method with truncated subspace sampling (tSS-BO) to tackle high-dimensional optimization challenges for large-scale analog circuit sizing. To address the high-dimensional challenges, we propose subspace sampling subject to a truncated Gaussian distribution. This approach limits the effective sampling dimensionality down to a constant upper bound, independent of the original dimensionality, leading to a significant reduction in complexity associated with the curse of dimensionality. The distribution covariance is iteratively updated using a truncated flow, where approximate gradients and center steps are integrated with decaying prior subspace features. We introduce gradient sketching and local Gaussian process (GP) models to approximate gradients without additional simulations to mitigate systematic errors. To enhance efficiency and ensure compatibility with constraints, we utilize local GP models for the selection of promising candidates, avoiding the cost of acquisition function optimization. The proposed tSS-BO method exhibits clear advantages over state-of-the-art methods in experimental comparisons. In synthetic benchmark functions, the tSS-BO method achieves up to $4.93\times$ evaluation speedups and a remarkable over $30\times$ algorithm complexity reduction compared to the Bayesian baseline. In real-world analog circuits, our method achieves up to $2\times$ speedups in simulation number and runtime.

关键词： Adaptation models Upper bound Runtime Systematics Optimization methods Gaussian processes Analog circuits

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Novel Multifunctional Transient Voltage Suppressor technology for Modular EOS/ESD Protection Circuit Designs 35

Novel Multifunctional Transient Voltage Suppressor Technolog...

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35th International Symposium on Power Semiconductor devices and ICs, ISPSD 2023

作者： Qi, Zhao Qiao, Ming Wei, Jingqi Shi, Yonggang Chen, Hongquan Li, Zhaoji Zhang, Bo University of Electronic Science and Technology of China State Key Laboratory of Electronic Thin Films and Integrated Devices Chengdu China Chongqing Institute of Microelectronics Industry Technology Uestc Chongqing China Institute of Electronic and Information Engineering of Uestc in Guangdong Dongguan China Shenzhen Institute for Advanced Study University of Electronic Science and Technology of China Shenzhen China

ISBN: (纸本)9798350396829

Transient voltage suppressor (TVS) is a kind of widely-used protection device which can enhance system surge and electrostatic discharge (ESD) robustness in small PCB area. However, different TVS cannot be fabricated using same technology due to the huge characteristic difference, which brings technology complexity in multifunctional system. In order to unity the TVS designs, a novel multifunctional TVS technology which solves non-uniformity finger triggering, voltage stacking and low leakage modular assembly issues is proposed. By using this TVS technology, the low-capacitance TVS array gets the peak current (IPP)of 5 A under the line-line capacitance (CL-L) of 0.25 pF, 5 V power clamp gets the IPP of 10 A with the dynamic resistance (Rdyn) of 0.15 Ohm, high-voltage protection diode gets the breakdown voltage (BV) of 70 V by stacking eight units and the surge TVS realizes IPP of 320 A by increasing finger amount without non-uniformity triggering. © 2023 IEEE.

关键词： Capacitance

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Analysis of SiC Damage Associated with Single-Event Gate Oxide Damage

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IEEE Transactions on Nuclear Science 2025年

作者： Qiu, Leshan Bai, Yun Chen, Yan Dong, Zewei Ding, Jieqin Hao, Jilong Tang, Yidan Tian, Xiaoli Liu, Xinyu Institute of Microelectronics of the Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences School of Integrated Circuits Beijing100049 China Zhuzhou CRRC Times Semiconductor Company Ltd State Key Laboratory of Advance Power Semiconductor Device Zhuzhou412001 China

This paper presents observations of SiC damage related to single-event gate oxide damage in SiC MOSFETs subjected to varying drain biases following heavy-ion irradiation and electrical stress. At low and medium drain biases, both surface melted and lattice damages in SiC were detected by transmission electron microscopy (TEM). While at high drain bias, crack damage propagation into the epilayer was observed directly by Scanning electron microscopy (SEM). Despite the differing types of observed SiC damage, all were confined beneath the gate oxide damage or latent damage induced by heavy ion strikes. Numerical simulations indicate that after gate oxide rupture, the formation of a gate-drain leakage path increases the current beneath the damaged oxide, leading to localized heating and subsequent SiC degradation and damage. These findings provide valuable insights for understanding the failure mechanisms of SiC MOSFETs subjected to single-event failures. © 1963-2012 IEEE.

关键词： High resolution transmission electron microscopy

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On the Reliability and Security Enhancements of Double-RIS Enabled WPC System with Jamming

On the Reliability and Security Enhancements of Double-RIS E...

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IEEE Conference on Wireless Communications and Networking

作者： Jingyu Chen Kunrui Cao Lu Lv Beixiong Zheng Haolian Chi Siwei Tang Danyu Diao School of Information and Communications National University of Defense Technology China State Key Laboratory of Integrated Services Networks Xidian University China School of Microelectronics South China University of Technology China

ISBN: (数字)9798350303582

ISBN: (纸本)9798350303599

This paper studies the physical layer security for a double reconfigurable intelligent surface (RIS) aided wireless powered communication system in the presence of an eaves-dropper, where a user acts as friendly jammer (J) to emit the artificial noise to improve the transmission security of another user. In particular, three RIS transmission schemes are proposed: 1) In scheme-I, both RISs are designed as optimal phase shift of wireless user (U); 2) In scheme-II, the first RIS is designed as optimal phase shift of U and the second RIS is designed as optimal phase shift of J, respectively; 3) In scheme-III, the first RIS is designed as optimal phase shift of J and the second RIS is designed as optimal phase shift of U, respectively. To reveal the achieved reliability and security performance of proposed three schemes, we analyze the connection outage probability (COP) and secrecy outage probability (SOP), respectively. The results show that scheme-II and scheme-III have the same COP performance and both of them are worse than scheme-I. The scheme-III achieves the best SOP performance, while scheme-I achieves the worst SOP performance that is slightly inferior to scheme-II.

关键词： Wireless communication Noise Reconfigurable intelligent surfaces Probability Physical layer security Power system reliability Security

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Two-Dimensional Thermal-Induced Warpage Prediction for Multi-Chiplet Heterogeneous Integration System in Advanced Packaging

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IEEE Transactions on Components, Packaging and Manufacturing technology 2025年

作者： Cao, He Xu, Qinzhi Liu, Jianyun Li, Zhiqiang Wang, Chenghan Ma, Xiaoning An, Kunlong Zhang, Daoqing Sun, Tunan State Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing100029 China EDA Center Institute of Microelectronics of the Chinese Academy of Sciences Beijing100029 China School of Integrated Circuits University of Chinese Academy of Sciences Beijing100049 China Beijing Key Laboratory of Three Dimensional and Nanometer Circuit Design Automation Technology Beijing100029 China

Thermal-induced warpage is a bottleneck problem in advanced packaging technology. In this paper, a new way of predicting the warpage deformation is proposed for multi-chiplet heterogeneous integration system, where the system deformations are considered as the combined actions of several asymmetric trimaterial assemblies based on the superposition principle. Firstly, an analytical model for an asymmetric tri-material assembly is derived by the beam theory. The rotation and rigid translation behaviors are investigated for the asymmetrical structures, which are determined by both the geometrical structures and the material properties. Secondly, the finite element method (FEM) is adopted to validate the analytical model and obtain the sample data. Then, the unknown parameters in the analytical model are extracted by the random forest algorithm (RF). Finally, a data-driven scale factor is introduced to modify the analytical model and improve its accuracy. The superposition warpage deformation of a heterogeneous integration system with 14 chiplets predicted by the present analytical model shows a good agreement with the FEM results with high efficiency. Therefore, the new thermal-induced warpage prediction method has a good potential of executing warpage analysis and package design of the multi-chiplet heterogeneous integration system in advanced packaging. © 2011-2012 IEEE.

关键词： Analytical models

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LauWS: Local Adaptive Unstructured Weight Sparsity of Load Balance for DNN in Near-Data Processing

LauWS: Local Adaptive Unstructured Weight Sparsity of Load B...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Zixu Li Wang Wang Xin Zhong Manni Li Jiayu Yang Yinyin Lin Guhyun Kim Yosub Song Chengchen Wang Xiankui Xiong State Key Laboratory of Integrated Chips and Systems School of Microelectronics Fudan University Shanghai China Solution Development Division SK Hynix Inc. South Korea State Key Laboratory of Mobile Multimedia Technology ZTE Corporation Shenzhen China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Memory wall issue has become the overwhelming bottleneck of future systems due to the explosive parameter growth and low computing density large language model (LLM). Near-data processing (NDP) could alleviate data traffic and energy consumption, but the storage demand of LLM is still enormous. Weight sparsity is helpful for reducing data capacity. Unstructured sparsity sacrifices less accuracy compared to structured one, but the random non-zero values distribution in NDP leads to load imbalance among parallel processing units. Here we propose LauWS which is seamlessly combined into various prior arts of sparsity. LauWS follows the local characteristics of feature distribution in weight matrix for various models, preserving even tiny features and discarding non-feature values as far as possible region by region. That is the key for LauWS achieving a trade-off between high prune ratio (PR) and less accuracy loss (AL). Evaluations are carried out based on a GDDR6-based bank-NDP system. The typical optimization compared to the no-prune includes 38% speedup at 0.8PR with no AL for MLP, 22.7% speedup at 0.5PR with no AL for GPT-2, 23.6% speedup at 0.5PR with the lowest perplexity for OPT-125m.

关键词： Energy consumption Accuracy Art Adaptive systems Circuits and systems Parallel processing Explosives

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