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A Valuable and Low-Budget Process Scheme of Equivalized 1 nm technology Node Based on 2D Materials

Nano-Micro Letters 2025年第8期17卷 294-305页

作者： Yang Shen Zhejia Zhang Zhujun Yao Mengge Jin Jintian Gao Yuhan Zhao Wenzhong Bao Yabin Sun He Tian College of Integrated Circuit Science and Engineering Shanghai Key Laboratory of Multidimensional Information ProcessingEast China Normal UniversityShanghai 200241People’s Republic of China Institute of Microelectronics and Beijing National Research Center for Information Science and Technology(BNRist) Tsinghua UniversityBeijing 100084People’s Republic of China State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433People’s Republic of China Shaoxin Laboratory Shaoxing 312000People’s Republic of China

Emerging two-dimensional(2D)semiconductors are among the most promising materials for ultra-scaled transistors due to their intrinsic atomic-level *** the stacking process advances,the complexity and cost of nanosheet field-effect transistors(NSFETs)and complementary FET(CFET)continue to *** 1 nm technology node is going to be based on Si-CFET process according to international roadmap for devices and systems(IRDS)(2022,https://***/),but not publicly confirmed,indicating that more possibilities still *** miniaturization advantage of 2D semiconductors motivates us to explore their potential for reducing process costs while matching the performance of next-generation nodes in terms of area,power consumption and *** this study,a comprehensive framework is built.A set of MoS2 NSFETs were designed and fabricated to extract the key parameters and *** then for benchmarking,the sizes of 2D-NSFET are scaled to a extent that both of the Si-CFET and 2D-NSFET have the same average device *** these conditions,the frequency of ultra-scaled 2D-NSFET is found to improve by 36%at a fixed power *** work verifies the feasibility of replacing silicon-based CFETs of 1 nm node with 2D-NSFETs and proposes a 2D technology solution for 1 nm nodes,i.e.,“2D eq 1 nm”*** the same time,thanks to the lower characteristic length of 2D semiconductors,the miniaturized 2D-NSFET achieves a 28%frequency increase at a fixed power ***,developing a standard cell library,these devices obtain a similar trend in 16-bit RISC-V *** work quantifies and highlights the advantages of 2D semiconductors in advanced nodes,offering new possibilities for the application of 2D semiconductors in high-speed and low-power integrated circuits.

关键词： Two-dimensional semiconductors 1 nm technology node Nanosheet field-effect transistors Complementary field-effect transistors Horizontal scaling

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Improvement of Ga_(2)O_(3)vertical Schottky barrier diode by constructing NiO/Ga_(2)O_(3)heterojunction

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Journal of Semiconductors 2024年第4期45卷 63-68页

作者： Xueqiang Ji Jinjin Wang Song Qi Yijie Liang Shengrun Hu Haochen Zheng Sai Zhang Jianying Yue Xiaohui Qi Shan Li Zeng Liu Lei Shu Weihua Tang Peigang Li School of Integrated Circuits&State Key Laboratory of Information Photonics and Optical Communications Beijing University of Posts and TelecommunicationsBeijing 100876China College of Integrated Circuit Science and Engineering Nanjing University of Posts and TelecommunicationsNanjing 210023China Beijing Microelectronics Technology Institute Beijing 100076China

The high critical electric field strength of Ga_(2)O_(3)enables higher operating voltages and reduced switching losses in power electronic *** Schottky metals and epitaxial films are essential for further enhancing device *** this work,the fabrication of vertical Ga_(2)O_(3)barrier diodes with three different barrier metals was carried out on an n--Ga_(2)O_(3)homogeneous epitaxial film deposited on an n+-β-Ga_(2)O_(3)substrate by metal-organic chemical vapor deposition,excluding the use of edge *** ideal factor,barrier height,specific on-resistance,and breakdown voltage characteristics of all devices were investigated at room *** addition,the vertical Ga_(2)O_(3)barrier diodes achieve a higher breakdown volt-age and exhibit a reverse leakage as low as 4.82×10^(-8)A/cm^(2)by constructing a NiO/Ga_(2)O_(3)***,Ga_(2)O_(3)power detailed investigations into Schottky barrier metal and NiO/Ga_(2)O_(3)heterojunction of Ga_(2)O_(3)homogeneous epitaxial films are of great research potential in high-efficiency,high-power,and high-reliability applications.

关键词： Ga_(2)O_(3) Schottky barrier diode NiO/Ga_(2)O_(3)heterojunction

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Linear Tuning of Positive Threshold Voltage in IGZO Thin-Film Transistors via Gate Dielectric Stack Engineering

IEEE Electron Device Letters

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IEEE Electron device Letters 2025年第5期46卷 781-784页

作者： Yan, Gangping Yang, Yanyu Tai, Lu Chen, Yuting Ma, Xueli Xiang, Jinjuan Xu, Gaobo Wang, Guilei Yin, Huaxiang Zhao, Chao Beijing Superstring Academy of Memory Technology Beijing100176 China Institute of Microelectronics of the Chinese Academy of Sciences State Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing100029 China University of Chinese Academy of Sciences School of Integrated Circuits Beijing100049 China

The positive threshold voltage (VTH) tuning in InGaZnO (IGZO) thin-film transistors (TFTs) has become an urgent issue. In this work, the effect of different ultrathin gate dielectric interlayers (ILs) inserted between the high-κ HfO2 and IGZO is investigated based on the pristine VTH of +0.064 V optimized by IGZO sputtering and post-annealing. By specifically combining varying HfO2 thicknesses and IL types, this initial VTH is linearly modulated to +0.528 V in IGZO devices without noticeable sub-threshold swing (SS) and mobility degradation. Attributed to the dipole and fixed charge modulation at the interface, the devices with 7-nm HfO2 and 2-nm SiO2 IL exhibit optimal results, including the most positive VTH, a decent mobility of 12 cm2/Vċ s, a well-maintained SS of 84.7 mV/dec, and promoted positive and negative bias stress (PBS/NBS) stability. This VTH modulation technique provides useful guidance for 3D integration such as IGZO 3D-DRAM with high performance. © 1980-2012 IEEE.

关键词： Thin film transistors

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Recent developments in nonferrous metals and related materials for biomedical applications in China:a review

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Rare Metals 2022年第5期41卷 1410-1433页

作者： Hai-Ling Tu Hong-Bin Zhao Yan-Yan Fan Qing-Zhu Zhang State Key Laboratory of Advanced Materials for Smart Sensing GRINM Group Co.Ltd.Beijing 100088China China Academy of Space Technology Beijing 100094China Key Laboratory of Microelectronics Devices&Integrated Technology Institute of MicroelectronicsCASBeijing 100029China

Biomedical materials have received increasing attention in recent decades and have been used in medical applications to advance patient care,such as prosthetic implants,tissue repair and regeneration,drug delivery systems,pharmaceutical or biological therapy products,and sensitive diagnostic *** different types of biomedical materials,nonferrous metals and related materials(NMRMs)are important and attractive *** updating of biomedical NMRMs and devices heavily relies on original research and applicationoriented ***,we provide recent research findings and succinct insights into the developments in NMRMs for biomedical applications in China,including the use of titanium,magnesium,copper,zinc,cobalt,zirconium,hafnium,niobium,rhenium,tantalum,tungsten,silver,gold,platinum,palladium,their alloys and compounds,rare earths,high-entropy alloys,and liquid ***,the literature review concludes with several possible directions of NMRMs for new and future developments in biomedical engineering.

关键词： Nonferrous metal Biomedical Implants In vitro and in vivo Imaging Cancer treatment

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P-type ionization level lowering in ultrawide bandgap Al1−xGaxN[112¯0] digital alloys

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Physical Review B 2024年第3期110卷 035202-035202页

作者： Xinhao Wang Jiaduo Zhu Wei Shang Shengrui Xu Liuying Fu Jincheng Zhang Yue Hao State Key Laboratory of Wide Bandgap Semiconductor Devices and Integrated Technology School of Microelectronics

Efficient p-type doping is essential and challenging for applications of ultra-wide-bandgap AlGaN with a high aluminum content. Although the band-edge-assisted ionization enabled by the superlattice of [0001] origination can reduce the ionization level due to the raised valence band maximum (VBM), the indispensable electric field induced by the spontaneous and piezoelectric polarization is in the entire range of alloy and quite negative to the photoelectric applications. In this work, we propose that band-edge-assisted ionization can be activated even without the universal electric field, which forms an ultralow ionization level of −0.1 eV for the Al0.8Ga0.2N[112¯0] digital alloy. The energy reduction is triggered by two factors: the intensive VBM states dominated by the coupling between GaN layers and the intriguing decrease in the unoccupied pz level, which is induced by a symmetry reduction from C3v-like to Cs at the dopant site. The transition of symmetry is triggered by a perturbation from the GaN layers, which is caused by a chainlike coupling of px states between nitrogen at the VBM and dopant sites and can be partially canceled depending on the dopant sites. In addition to the conventional band bending in band-edge-assisted ionization, the reduction of ionization level activated by long-ranged orbital coupling offers a new view for efficient p-type doping in AlGaN systems.

关键词： Dopants Electronic structure First-principles calculations Impurities

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1.27 GW/cm² Reverse Blocking E-Mode GaN-Si(100) Monolithic Heterogeneous Integration Cascode Switch With Ultralow Turn-On Voltage and Dynamic RON

IEEE Electron Device Letters

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IEEE Electron device Letters 2025年第5期46卷 805-808页

作者： Fan, Yutong Zhang, Weihang Zhang, Yachao Wu, Yinhe Feng, Xin Liu, Zhihong Jiang, Yang In Mak, Pui Hao, Yue Zhang, Jincheng Xidian University National Key Laboratory of Wide Bandgap Semiconductor Devices and Integrated Technology School of Microelectronics Xi'an710071 China Guangzhou Institute of Technology Xidian University Guangzhou Wide Bandgap Semiconductor Innovation Center Guangzhou510555 China Institute of Microelectronics University of Macau State Key Laboratory of Analog and Mixed-Signal Vlsi China

In this letter, an E-Mode GaN-Si(100) monolithic heterogeneous integration cascode switch (RBMHIC-switch) with reverse blocking compatibility on a SiC substrate with an AlN buffer layer is demonstrated. The RBMHIC-switch with LGD of 22~μ m showed a threshold voltage (VTH) of 2.64 V, a large forward gate voltage swing of 16.27 V, a turn-on voltage (VON) of 0.3 V, and an extremely low reverse leakage current (IR) of 3.5× 10-4 mA/mm at -2000 V. The forward breakdown voltage (VFBR) of 2264 V and reverse breakdown voltage (VRBR) of 2183 V with a specific on-resistance (RON, SP ) of 3.74 mΩ ċ cm2 were achieved, resulting in a forward power figure of merit (PFOM = V BR2 /RON,SP) of 1.35 GW/cm2 and reverse PFOM of 1.27 GW/cm2. The ratio between dynamic-RON and static-RON was 1.104 and 1.127 after a 10 ms 1900 V drain stress voltage (V DS- OFF ) and a 10 ms -1900 V V DS- OFF (delay time = 1~μ s) for the RBMHIC-switches, respectively, which were the best among all existing GaN power devices with reverse blocking capability. The thermal resistance at different temperatures was also extracted. The RBMHIC-switche shows decent overall characteristics as compared to the reported results. © 1980-2012 IEEE.

关键词： Gallium nitride

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FSMM: An Efficient Matrix Multiplication Accelerator Supporting Flexible Sparsity 24

FSMM: An Efficient Matrix Multiplication Accelerator Support...

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43rd International Conference on Computer-Aided Design, ICCAD 2024

作者： Qiao, Yuxuan Yang, Fan Zhang, Yecheng Xiong, Xiankui Yao, Xiao Yao, Haidong State Key Laboratory of Integrated Chips and Systems Fudan University Shanghai China School of Microelectronics Fudan University Shanghai China State Key Laboratory of Mobile Network and Mobile Multimedia Technology ZTE Corporation Shenzhen China

ISBN: (纸本)9798400710773

Sparse matrix multiplication is a critical operation in deep learning. However, matrix sparsity leads to irregular data flow, which would degrade the efficiency of matrix multiplication. Traditional accelerators, equipped with additional hardware units to address this issue, often experience the issue of low hardware utilization. Furthermore, N : M structured sparsity and corresponding hardware architectures face challenges such as accuracy degradation, limited flexibility, and restricted applicability. In this paper, we propose a Flexible Sparse Matrix Multiplication Accelerator (FSMM), which can improve the efficiency of sparse matrix multiplication through both algorithmic-level and hardware-level optimizations. At the algorithmic level, we propose the matrix-matrix multiplication with block-level outer production and fine-grained matrix reordering algorithm. The algorithm balances the sparsity of each column of a matrix block, which improves matrix compression, balances the load, and speeds up computation. This algorithm reduces storage by 8.2% ~ 85.9%. At the hardware-level, we introduce a flexible architecture for matrix multiplication. It selects the most suitable data path to complete matrix multiplication based on the sparsity of the reordered matrix. FSMM achieves a speedup of 1.90× ~ 16.18× over Systolic Array and 1.70× ~ 2.87× over the existing TSTC approach. © 2024 Copyright is held by the owner/author(s).

关键词： Fast response computer systems

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Enhancement of fMAX of InP-based HEMTs by double-recessed offset gate process

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Chinese Physics B 2022年第5期31卷 743-748页

作者： Bo Wang Peng Ding Rui-Ze Feng Shu-Rui Cao Hao-Miao Wei Tong Liu Xiao-Yu Liu Hai-Ou Li Zhi Jin Guangxi Key Laboratory of Precision Navigation Technology and Application Guilin University of Electronic TechnologyGuilin 541004China High-Frequency High-Voltage Device and Integrated Circuits Center Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China

A double-recessed offset gate process technology for In P-based high electron mobility transistors(HEMTs)has been developed in this ***-recessed and double-recessed HEMTs with different gate offsets have been fabricated and *** with single-recessed devices,the maximum drain-source current(I_(D,max))and maximum extrinsic transconductance(g_(m,max))of double-recessed devices decreased due to the increase in series ***,in terms of RF performance,double-recessed HEMTs achieved higher maximum oscillation frequency(f_(MAX))by reducing drain output conductance(g_(m,max))and drain to gate capacitance(C_gd).In addition,further improvement of fMAXwas observed by adjusting the gate offset of double-recessed *** can be explained by suppressing the ratio of C_(gd)to source to gate capacitance(C_gd)by extending drain-side recess length(Lrd).Compared with the single-recessed HEMTs,the f;of double-recessed offset gate HEMTs was increased by about 20%.

关键词： InP HEMT maximum oscillation frequency(fMAX) double-recess offset gate

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Short-term prediction for chaotic time series based on photonic reservoir computing using VCSEL with a feedback loop

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Photonics Research 2024年第6期12卷 1222-1230页

作者： XINGXING GUO HANXU ZHOU SHUIYING XIANG QIAN YU YAHUI ZHANG YANAN HAN TAO WANG YUE HAO State Key Laboratory of Integrated Service Networks Xidian UniversityXi'an 710071China State Key Discipline Laboratory of Wide Bandgap Semiconductor Technology School of MicroelectronicsXidian UniversityXi'an 710071China

Chaos,occurring in a deterministic system,has permeated various fields such as mathematics,physics,and life ***,the prediction of chaotic time series has received widespread attention and made signifi-cant ***,many problems,such as high computational complexity and difficulty in hardware im-plementation,could not be solved by existing *** overcome the problems,we employ the chaotic system of a vertical-cavity surface-emitting laser(VCSEL)mutual coupling network to generate chaotic time series through optical system simulation and experimentation in this ***,a photonic reservoir com-puting based on VCSEL,along with a feedback loop,is proposed for the short-term prediction of the chaotic time *** relationship between the prediction difficulty of the reservoir computing(RC)system and the differ-ence in complexity of the chaotic time series has been studied with ***,the attention coefficient of injection strength and feedback strength,prediction duration,and other factors on system perfor-mance are considered in both simulation and *** use of the RC system to predict the chaotic time series generated by actual chaotic systems is significant for expanding the practical application scenarios of the RC.

关键词： loop chaotic prediction

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Experimental Demonstration of A CT-FeFET Array with Intrinsic Long-Short-Term Plasticity for Low-Cost Trajectory Prediction

Experimental Demonstration of A CT-FeFET Array with Intrinsi...

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2024 IEEE International Electron devices Meeting, IEDM 2024

作者： Li, Chao Yu, Jie Zhang, Xumeng Zhang, Zhaohao Zhu, Fangduo Ouyang, Siyuan Chen, Pei Cheng, Lingli Xu, Gaobo Zhang, Qingzhu Yin, Huaxiang Liu, Qi Liu, Ming State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200438 China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing100029 China

ISBN: (纸本)9798350365429

Trajectory prediction is a vital function in the auto-driving field, typically achieved with a long short-term memory network. Static IMC technology accelerates the computing of long-term parameters, while the execution of short-term parameters faces great buffer overhead. Inspired by the fused long-short-term synaptic plasticity in biology, here, we proposed a dynamic IMC strategy based on a charge-trapping FeFET array with intrinsic long-short-term plasticity. The long-term weights are stored in the ferroelectric domain, while the short-term weights are in-situ dynamically operated in a charge-trapping domain, eliminating the external caching process. We further demonstrated a dynamic IMC neuromorphic system built on this array for performing trajectory prediction of moving vehicles, achieving more than 1000× and 4× improvements than GPU in power consumption and memory overhead. © 2024 IEEE.

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