High precision and large dynamic range measurement ave required in the readout systems for the Water Cherenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO). This paper presents ...
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High precision and large dynamic range measurement ave required in the readout systems for the Water Cherenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO). This paper presents a prototype of a 12-bit 40 MSPS Analog-to-Digital Converter (ADC) Application Specific Integrated Circuit (ASIC) designed for the readout of the LHAASO WCDA. Combining this ADC and the front-end ASIC finished in our previous work, high precision charge measurement can be achieved based on the digital peak detection method. This ADC is implemented based on a power-efficient Successive Approximation Register (SAR) architecture, which incorporates key parts such as a Capacitive Digital-to-Analog Converter (CDAC), dynamic compavator and asyn- chronous SAR control logic. The simulation results indicate that the Effective Number Of Bits (ENOB) with a sampling rate of 40 MSPS is better than 10 bits in an input frequency range below 20 MHz, while its core power consumption is 6.6 mW per channel. The above results are good enough for the readout requirements of the WCDA.
This article presents a prototype of beam position and phase measurement(BPPM)electronics designed for the LINAC in China Accelerator Driven Sub-critical system(ADS).The signals received from the Beam Position Monitor...
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This article presents a prototype of beam position and phase measurement(BPPM)electronics designed for the LINAC in China Accelerator Driven Sub-critical system(ADS).The signals received from the Beam Position Monitor(BPM)detectors are narrow pulses with a repetition frequency of 162.5 MHz and a dynamic range more than40 *** on the high-speed high-resolution Analog-to-Digital conversion technique,the input RF signals are directly converted to In-phase and Quadrature-phase(IQ)streams through under-sampling,which simplifies both the analog and digital processing *** signal processing is integrated in one single FPGA,in which real-time beam position,phase and current can be obtained.A series of simulations and tests have been conducted to evaluate the *** test results indicate that this prototype achieves a phase resolution better than 0.1 degree and a position resolution better than 20μm over a 40 dB dynamic range with the bandwidth of 780 kHz,which is well beyond the application requirements.
High precision time measurement is required in the readout of the neutron wall and TOF walls in the external target experiment of the Cooling Storage Ring(CSR) project in the Heavy Ion Research Facility in Lanzhou(HIR...
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High precision time measurement is required in the readout of the neutron wall and TOF walls in the external target experiment of the Cooling Storage Ring(CSR) project in the Heavy Ion Research Facility in Lanzhou(HIRFL).Considering the time walk correction,both time and charge are measured in the readout *** this 16-channel measurement module,time and charge information are digitized by TDCs at the same time based on the Time-Over-Threshold(TOT) method;meanwhile,by employing high-density ASIC chips,the electronics complexity is effectively *** results indicate that this module achieves a time resolution better than 25 ps and a charge resolution better than 5%over the input amplitude range from 50 mV to 3V.
The Large Area Water Cherenkov Array (LAWCA) experiment focuses on high energy gamma astronomy between 100 GeV and 30 TeV. Invoked by the idea of hardware triggerless structure, a prototype of LAWCA trigger electron...
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The Large Area Water Cherenkov Array (LAWCA) experiment focuses on high energy gamma astronomy between 100 GeV and 30 TeV. Invoked by the idea of hardware triggerless structure, a prototype of LAWCA trigger electronics is implemented in one single VME-9U module which obtains all the data from the 100 Front End Electronic (FEE) endpoints. Since the trigger electronics accumulate all the information, the flexibility of trigger processing can be improved. Meanwhile, the dedicated hardware trigger signals which are fed back to front end are eliminated; this leads to a system with better simplicity and stability. To accommodate the 5.4 Gbps system average data rate, the fiber based high speed serial data transmission is adopted. Based on the logic design in one single FPGA device, real-time trigger processing is achieved; the reprogrammable feature of the FPGA device renders a reconfigurable structure of trigger electronics. Simulation and initial testing results indicate that the trigger electronics prototype functions well.
A photon conversion finder (PCF) based on track information from the main drift chamber (MDC) of the Beijing Spectrometer (BESⅢ) at the Beijing Electron Positron Collider (BEPCⅡ) is developed. The validation...
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A photon conversion finder (PCF) based on track information from the main drift chamber (MDC) of the Beijing Spectrometer (BESⅢ) at the Beijing Electron Positron Collider (BEPCⅡ) is developed. The validation of the PCF is done by reconstructing π 0 and measuring the branching fraction of J/ψ→γη . Using the developed PCF tool, we mapped the materials from the interaction point through the BEPCII beam pipe up to the inner wall of the MDC.
An automatic clock synchronization method implemented in a field programmable gate array (FPGA) is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight (E...
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An automatic clock synchronization method implemented in a field programmable gate array (FPGA) is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight (ETOF) upgrade of the Beijing Spectrometer (BESIII). In this design, an FPGA is used to automatically monitor the synchronization circuit and deal with signals coming from the external clock synchronization circuit. By testing different delay time of the detection signal and analyzing the signal state returned~ the synchronization windows can be found automatically by the FPGA. The new clock system not only retains low clock jitter which is less than 20ps root mean square (RMS), but also demonstrates automatic synchronization to the beam bunches. So far, the clock auto-synchronizing function has been working successfully under a series of tests. It will greatly simplify the system initialization and maintenance in the future.
The experimental muon source on China Spallation Neutron Source(CSNS) is expected to be a high intensity(105μ+/s) surface muon source with a small beam spot of 4-cm *** a practical application of this muon source,we ...
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The experimental muon source on China Spallation Neutron Source(CSNS) is expected to be a high intensity(105μ+/s) surface muon source with a small beam spot of 4-cm *** a practical application of this muon source,we are devoting to develop the first pulsed μSR spectrometer in *** this paper,the performance of plastic scintillators in the μSR spectrometer is studied by Monte Carlo *** processes such as positron energy deposition,scintillation photons production,light propagation and photon-electron conversion are carefully *** to the results,an optimal dimension of the plastic scintillator is proposed using for our future spectrometer,which has a long-strip shape with the dimension variation range of 50–60 mm length,5–8 mm height,and 10–12 mm ***,we can build a spectrometer with a count rate up to 104e+/s by 100–120 forward and backward segmental detectors in *** simulation could serve as an important guide for spectrometer construction.
High-purity germanium (HPGe) detectors are well suited to analyse the radioactivity of samples. In order to reduce the environmental background for an ultra-low background HPGe spectrometer, low-activity lead and ox...
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High-purity germanium (HPGe) detectors are well suited to analyse the radioactivity of samples. In order to reduce the environmental background for an ultra-low background HPGe spectrometer, low-activity lead and oxygen free copper are installed outside the probe to shield from gamma radiation, with an outer plastic scintillator to veto cosmic rays, and an anti-Compton detector to improve the peak-to-Compton ratio. Using Geant4 tools and taking into account a detailed description of the detector, we optimize the sizes of these detectors to reach the design requirements. A set of experimental data from an existing HPGe spectrometer was used to compare with the simulation. For the future low-background HPGe detector simulation, considering different thicknesses of BGO crystals and anti-coincidence efficiency, the simulation results show that the optimal BGO thickness is 5.5 cm, and the peak-to-Compton ratio of 40K is raised to 1000 when the anti-coincidence efficiency is 0.85. In the background simulation, 15 cm oxygen-free copper plus 10 cm lead can reduce the environmental gamma rays to 0.0024 cps/100 cm3 Ge (50 keV-2.8 MeV), which is about 10-5 of the environmental background.
Systematic investigations including both simulation and prototype tests have been done about the interpolating resistive readout structure with GEM (Gaseous Electron Multiplier) detector. From the simulation, we hav...
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Systematic investigations including both simulation and prototype tests have been done about the interpolating resistive readout structure with GEM (Gaseous Electron Multiplier) detector. From the simulation, we have a good knowledge of the process of charge diffusion on the surface of the readout plane and develop several reconstruction methods to determine the hit position. The total signal duration time of a typical event with the readout structure was about several hundred nanoseconds, which implied an ideal count rate up to 106 Hz. A stable working prototype was designed and fabricated after the simulation. Using 55Fe 5.9 performance of the prototype was examined with flat field image and some special geometry energy resolution of about 17% was obtained. keV X-ray, the image shapes, meanwhile, an
We first clarify timing issues of non-uniform sampling intervals regarding a 5 GS/s fast pulse sampling module with DRS4. A calibration strategy is proposed, and as a result, the waveform timing performance is improve...
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We first clarify timing issues of non-uniform sampling intervals regarding a 5 GS/s fast pulse sampling module with DRS4. A calibration strategy is proposed, and as a result, the waveform timing performance is improved to below 10 ps RMS. We then further evaluate waveform-timing performance of the module by comparing with a 10 GS/s oscilloscope in a setup with plastic scintillators and fast PMTs. Different waveform timing algorithms are employed for analysis, and the module shows comparable timing performance with that of the oscilloscope.
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