检索结果-内蒙古大学图书馆

16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Li, Jiangnan Zheng, Su Wang, Lingli Yin, Wenbo Fudan University State Key Laboratory of Asic and System Department of Microelectronics Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Coarse-grained reconfigurable architecture (CGRA) accelerator is a promising solution in fields such as deep learning and edge computing. One of the difficult problems to design the accelerator is to map the data flow graph (DFG) to the architecture efficiently. The previous mapping algorithms based on graph structure mainly focus on optimization during the placement and routing stage, which may fall into a local minimum and lead to an increase in initiation interval (II). We propose a CGRA mapping algorithm, OrderMap, based on DFG analysis and graph homomorphism. It analyzes the DFG structure information to decide the node mapping order, followed by placement, and routing. Experimental results show that our algorithm is faster than CGRA-ME with smaller IIs. Compared with FastCGRA based on the depth-first order, OrderMap is 22.3 × faster with the same mapping results. © 2022 IEEE.

关键词： Deep learning

来源：评论

学校读者我要写书评

暂无评论

Contact optimisation strategy for wafer-scale field-effect transistors based on two-dimensional semiconductors

引用

Journal of Materials Science & Technology 2023年第2期133卷 230-237页

作者： Ling Tong Xiaojiao Guo Zhangfeng Shen Lihui Zhou Jingyi Ma Xinyu Chen Honglei Chen Yin Xia Chuming Sheng Saifei Gou Die Wang Xinyu Wang Xiangqi Dong Yuxuan Zhu Xinzhi Zhang David Wei Zhang Sheng Dai Xi Li Peng Zhou Yangang Wang Wenzhong Bao State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai 200433China College of Biological Chemical Science and EngineeringJiaxing UniversityJiaxing 314001China Key Laboratory for Advanced Materials and Feringa Nobel Prize Scientist Joint Research Center Institute of Fine ChemicalsSchool of Chemistry&Molecular EngineeringEast China University of Science and TechnologyShanghai 200237China State Key Laboratory of Surface Physics and Department of Physics Fudan UniversityShanghai 200433China

Two-dimensional(2D)semiconductors can be utilized to continually miniaturize nanoscale electronic ***,achieving a practical solution for satisfying electrical contact with 2D semiconductors remains *** this study,we developed a novel contact structure with transferred multilayer(t-ML)MoS 2 by integrating both edge and top *** in-situ plasma treatment for the edge of the MoS 2 channel and successive metal deposition,we achieved 16 times lower contact resistivity(22.8 kΩμm)than that of the top contacted *** thickness-dependent electrical measurement indicates that edge contact is highly effective with thick MoS 2 due to the alleviated current-crowding effect re-sulting from the small contact *** temperature-dependent transport measurement further confirms the effective minimization of the influence from the Schottky barrier and tunnelling ***,the simplified resistor network model and energy-band diagram were proposed to understand the carrier transport *** work provides a practical strategy for achieving excellent electrical contact between bulk metals and 2D semiconductors,paving the way for future large-scale 2D electronic devices.

关键词： Edge contact 2D materials Field-effect transistors Schottky barrier Contact resistance

来源：评论

学校读者我要写书评

暂无评论

A Dual-Mode Split-Based Calibration Technique for Time-Interleaved ADCs

A Dual-Mode Split-Based Calibration Technique for Time-Inter...

引用

International Conference on Communications, Circuits and systems (ICCCAS)

作者： Yuguo Xiang Danfeng Zhai Ye Wang Fan Ye State Key Laboratory of ASIC and System Fudan University Shanghai China

ISBN: (数字)9798350386271

ISBN: (纸本)9798350386288

This paper proposes a structure of spilt ADC which can be converted to a Time interleaved (TI) sampling mode to double the sampling rate. The architecture has two modes. In the split mode, two channels use the same clock, and through the split architecture the capacitor mismatch error, amplifier gain error, and timing skew are calibrated. After calibrate those nonideal factors, the TI mode is started. By shifting the phase of one clock 180-degree, the sampling rate is doubled. The architecture greatly reduces the complexity of the calibration algorithm and hardware consumption of time-interleaved ADC. The behavioral simulation shows llbit split ADC can be converted to TI ADC with double sampling rate which achieves 58dB SNDR, 78dB SFDR on average.

关键词： Circuits and systems Simulation Capacitors Hardware Calibration Timing Complexity theory

来源：评论

学校读者我要写书评

暂无评论

Increasing the Post Halo Implantation Anneal Temperature for the Effective Improvement of Threshold Voltage Roll-off Induced by the Unique Non-uniform Boron Diffusion from the Embedded Source/Drain

Increasing the Post Halo Implantation Anneal Temperature for...

引用

2022 China Semiconductor Technology International Conference, CSTIC 2022

作者： Li, Run-Ling Jiang, Yu-Long School of Microelectronics Fudan University State Key Laboratory of Asic and System Shanghai200433 China

ISBN: (数字)9781665497589

ISBN: (纸本)9781665497589

The severe threshold voltage (Vt) roll-off is revealed for PMOSFETs with the embedded SiGe source/drain (eSiGe S/D) when the gate length decreases. The unique non-uniform boron diffusion into the channel region from eSiGe is found to be the main reason, which is intrinsically caused by the sigma-shaped trench. Lowering the growth temperature of eSiGe is widely adopted to solve the Vt roll-off issue but with a very complicated adjustment of eSiGe growth process. Without the change of eSiGe growth process, a post halo implantation anneal at a higher temperature before the S/D trench etching is proposed and demonstrated to be able to effectively improve the Vt roll-off too, providing a new way to suppress short channel effect. © 2022 IEEE.

关键词： Threshold voltage

来源：评论

学校读者我要写书评

暂无评论

CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design

CFEACT: A CGRA-based Framework Enabling Agile CNN and Transf...

引用

International Conference on Field Programmable Logic and Applications

作者： Yiqing Mao Xuchen Gao Jiahang Lou Yunhui Qiu Wenbo Yin Wai-Shing Luk Lingli Wang State Key Laboratory of ASIC and System Fudan University Shanghai China

ISBN: (数字)9798331530075

ISBN: (纸本)9798331530082

Convolutional neural networks (CNNs) and transformer neural networks have been adopted in a wide range of applications such as natural language processing and computer vision. Coarse-grained reconfigurable architectures (CGRAs) are highly suitable for CNN and transformer applications due to their high flexibility and energy efficiency. However, current implementations of CGRA for CNNs and transformers have several limitations including the lack of system-on-Chip (SoC), insufficient support for nonlinear functions and the absence of a software toolchain. To address these challenges, we present CFEACT, a CGRA-based framework that enables agile development of CNN and transformer accelerators. CFEACT offers a broad design space of efficient CGRA accelerators through a highly flexible architecture template. The well-designed SoC, innovative mapping schemes, and comprehensive software toolchain offer a complete solution for implementing various CNN and transformer models on the generated CGRAs. Compared with the state-of-the-art works, accelerators generated by CFEACT can achieve more than $2 \times$ improvement in area-delay product for CNNs and an average of $2 \times$ higher performance for transformers.

关键词： Neural networks Transformers Software Hardware Natural language processing system-on-chip Space exploration Reconfigurable architectures Convolutional neural networks Logic

来源：评论

学校读者我要写书评

暂无评论

A General-Purpose Compiler Design for Instruction-Based AI Accelerator Implementation 15

A General-Purpose Compiler Design for Instruction-Based AI A...

引用

15th IEEE International Conference on asic, asicON 2023

作者： Wang, Mengxuan Linghu, Yuan Wu, Chang Fudan University State Key Laboratory of ASIC and System Shanghai China Shanghai Fudan Microelectronics Group Co. Ltd. Shanghai China

ISBN: (纸本)9798350312980

With the rapid advancement of deep neural networks, the automatic generation of accelerator design is a very important problem for the deployment of AI applications, especially for edge computation. In this paper, we propose a general purpose compiler design for instruction-based CNN accelerator design. Our compiler incorporates network pruning and quantization capabilities for better performance. CDFG-based layer fusion and scheduling are used for heterogeneous computing with consideration of data transformation and synchronization between CPU and accelerator. A device file is used to define the instruction set and data space so that our compiler supports various accelerator designs uniformly. We used our compiler to implement VGG16 and yolo2 in FPGAs and achieved better performance than existing designs. © 2023 IEEE.

关键词： Accelerator Compiler Instruction Scheduling

来源：评论

学校读者我要写书评

暂无评论

Sub-SA: Strengthen In-Context Learning via Submodular Selective Annotation 27

Sub-SA: Strengthen In-Context Learning via Submodular Select...

引用

27th European Conference on Artificial Intelligence, ECAI 2024

作者： Qian, Jian Sun, Miao Zhou, Sifan Zhao, Ziyu Hun, Ruizhi Chiang, Patrick State Key Laboratory of ASIC and System Fudan University Shanghai China School of Electrical and Electronic Engineering Nanyang Technological University Singapore School of Automation Southeast University Nanjing China

ISBN: (纸本)9781643685489

In-context learning (ICL) leverages in-context examples as prompts for the predictions of Large Language Models (LLMs). These prompts play a crucial role in achieving strong performance. However, the selection of suitable prompts from a large pool of labeled examples often entails significant annotation costs. To address this challenge, we propose Sub-SA (Submodular Selective Annotation), a submodule-based selective annotation method. The aim of Sub-SA is to reduce annotation costs while improving the quality of in-context examples and minimizing the time consumption of the selection process. In Sub-SA, we design a submodular function that facilitates effective subset selection for annotation and demonstrates the characteristics of monotonically and submodularity from the theoretical perspective. Specifically, we propose RPR (Reward and Penalty Regularization) to better balance the diversity and representativeness of the unlabeled dataset attributed to a reward term and a penalty term, respectively. Consequently, the selection for annotations can be effectively addressed with a simple yet effective greedy search algorithm based on the submodular function. Finally, we apply the similarity prompt retrieval to get the examples for ICL. Compared to existing selective annotation approaches, Sub-SA offers two main advantages. (1.) Sub-SA operates in an end-to-end, unsupervised manner, and significantly reduces the time consumption of the selection process (from hours-level to millisecond-level). (2.) Sub-SA enables a better balance between data diversity and representativeness and obtains state-of-the-art performance. Meanwhile, the theoretical support guarantees their reliability and scalability in practical scenarios. Extensive experiments conducted on diverse models and datasets demonstrate the superiority of Sub-SA over previous methods, achieving millisecond(ms)-level time selection and remarkable performance gains. The efficiency and effectiveness of Sub-SA make it

关键词：

来源：评论

学校读者我要写书评

暂无评论

Differences in MBUs induced by high-energy and medium-energy heavy ions in 28 nm FPGAs

引用

Nuclear Science and Techniques 2022年第9期33卷 28-36页

作者： Shuai Gao Jin-Hu Yang Bing Ye Chang Cai Ze He Jie Liu Tian-Qi Liu Xiao-Yu Yan You-Mei Sun Guo-Qing Xiao Institute of Modern Physics Chinese Academy of SciencesLanzhou 730000China University of Chinese Academy of Sciences Beijing 100049China State Key Laboratory of ASIC and System Fudan UniversityShanghai 201203China State Key Laboratory of Analog and Mixed-Signal VLSI University of MacaoMacao 999078China

Multiple-bit upsets(MBUs)have become a threat to modern advanced field-programmable gate arrays(FPGAs)applications in radiation ***,many investigations have been conducted using mediumenergy heavy ions to study the effects of MBU ***,high-energy heavy ions(HEHIs)greatly affect the size and percentage of MBUs because their ionizationtrack structures differ from those of medium-energy heavy *** this study,the different impacts of high-energy and medium-energy heavy ions on MBUs in 28 nm FPGAs as well as their mechanisms are thoroughly *** the Geant4 calculation,more serious energy effects of HEHIs on MBU scales were successfully *** addition,we identified worse MBU responses resulting from lowered *** MBU orientation effect was observed in the radiation of different *** broadened ionization tracks for tilted tests in different dimensions could result in different MBU *** results also revealed that the ionization tracks of tilted HEHIs have more severe impacts on the MBU scales than mediumenergy heavy ions with much higher linear energy ***,comprehensive radiation with HEHIs is indispensable for effective hardened designs to apply highdensity 28 nm FPGAs in deep space exploration.

关键词： FPGA High-energy heavy-ion radiation MBU Ionization track

来源：评论

学校读者我要写书评

暂无评论

PWL- Explorer: A Reconfigurable Architecture for Nonlinear Activation Function with Automatic DSE

PWL- Explorer: A Reconfigurable Architecture for Nonlinear A...

引用

Electronics Design Automation (ISEDA), International Symposium of

作者： Yiqing Mao Huizhen Kuang Wai-Shing Luk Lingli Wang State Key Laboratory of ASIC and System Fudan University Shanghai China

ISBN: (数字)9798350352030

ISBN: (纸本)9798350352047

Nonlinear functions are indispensable parts of deep neural networks (DNNs). Based on the piecewise approximation with the non-uniform segmentation strategy, this paper proposes PWL- Explorer, a highly parameterized reconfigurable nonlinear core designed with Chisel to implement diverse nonlinear functions. Additionally, we model the design space exploration (DSE) as a multi-objective black-box optimization problem via Bayesian optimization to explore the Pareto front of PWL- Explorer for the precision and area-delay product (ADP) objectives. The experimental results show that compared to state-of-the-art work for element-wise activation functions, the optimized PWL-Explorer architecture achieves an average of 1.58× better ADP while obtaining 2.93 × higher maximum absolute error (MAE) precision. Compared to state-of-the-art work for Softmax, PWL-Explorer achieves 1.05× better ADP while obtaining 40.01 x better mean square error (MSE) precision. Due to the elaborate hardware design and push-button workflow, PWL-Explorer can provide support to DNN accelerator developers.

关键词： Design automation Closed box Artificial neural networks Mean square error methods Hardware Space exploration Bayes methods

来源：评论

学校读者我要写书评

暂无评论

A Dynamically Reconfigurable VLSI Architecture for H.264 Integer Transforms

引用

Chinese Journal of Electronics 2023年第3期21卷 510-514页

作者： HONG Qi CAO Wei TONG Jiarong State Key Laboratory of ASIC and System Fudan University Shanghai China

The 4 ×4 integer transforms have been adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4 ×4 forward and inverse transforms for H.264 are deduced. A new dynamically reconfigurable architecture without transpose memory for the integer transforms is proposed on the basis of the new SFGs. In comparison with the existing designs, the number of computing elements can be cut down through dynamically reconfiguration in our design. Our design is implemented with 0.18µm CMOS technology. Under a clock frequency of 200 MHz, this architecture allows the real-time processing of 4096 × 2048 at 30 fps with the area cost of 5140 gates and the power dissipation of 15.64mW.

关键词： Video coding Costs Transforms Very large scale integration Logic gates Power dissipation Reconfigurable architectures

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：