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Research of Efficient Utilization Routing Algorithm for Current FPGA

Chinese Journal of Electronics 2023年第1期19卷 48-52页

作者： Ding Xie Jinmei Lai Jiarong Tong ASIC and System State Key Laboratory Fudan University Shanghai China

Current FPGAs contain routing resources of different lengths and connectivity, and the connection relation of which are described by hierarchical General routing matrix (GRM). In this paper, we present a practical routing algorithm which can represent the complex driving relationships contained in GRMs and utilize routing resources more efficient for GRM based FPGAs. First, we build Routing resource graph (RRG) by a bottom-up way, then employ A* directed search algorithm while dynamically updating the base cost of routing resource nodes, so that the utilization rate of routing resources can be enhanced, and this routing algorithm has high-adaptability to latest FPGA architectures. The experiment result shows that the utilization rate of hex lines and long lines has been raised by 6% and 8% respectively.

关键词： Costs Heuristic algorithms Routing Field programmable gate arrays

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Polarization-induced photocurrent switching effect in heterojunction photodiodes

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Nano Research 2023年第4期16卷 5503-5510页

作者： Dingbo Chen Yu-Chang Chen Guang Zeng Yu-Chun Li Xiao-Xi Li Dong Li Chao Shen Nan Chi Boon S.Ooi David Wei Zhang Hong-Liang Lu State Key Laboratory of ASIC and System Shanghai Institute of Intelligent Electronics&SystemsSchool of MicroelectronicsFudan UniversityShanghai 200433China Key Laboratory for Information Science of Electromagnetic Waves Department of Communication Science and EngineeringFudan UniversityShanghai 200433China Photonics Laboratory Division of ComputerElectricaland Mathematical Sciences and EngineeringKing Abdullah University of Science and Technology(KAUST)Thuwal 23955-6900Kingdom of Saudi Arabia

The unipolar photocurrent in conventional photodiodes(PDs)based on photovoltaic effect limits the output modes and potential versatility of these devices in *** photodiodes with photocurrent switching are emerging as a promising solution for obtaining photoelectric devices with unique and attractive functions,such as optical logic ***,we design an all-solid-state chip-scale ultraviolet(UV)PD based on a hybrid GaN heterojunction with engineered bipolar polarized electric *** introducing the polarization-induced photocurrent switching effect,the photocurrent direction can be switched in response to the wavelength of incident light at 0 V *** particular,the photocurrent direction exhibits negative when the irradiation wavelength is less than 315 nm,but positive when the wavelength is longer than 315 *** device shows a responsivity of up to−6.7 mA/W at 300 nm and 5.3 mA/W at 340 nm,*** particular,three special logic gates in response to different dual UV light inputs are demonstrated via a single bipolar PD,which may be beneficial for future multifunctional UV photonic integrated devices and systems.

关键词： GaN heterostructure ultraviolet(UV)photodiodes bipolar photocurrent optical logic device

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Top gate engineering of field-effect transistors based on wafer-scale two-dimensional semiconductors

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Journal of Materials Science & Technology 2022年第11期106卷 243-248页

作者： Jingyi Ma Xinyu Chen Yaochen Sheng Ling Tong Xiaojiao Guo Minxing Zhang Chen Luo Lingyi Zong Yin Xia Chuming Sheng Yin Wang Saifei Gou Xinyu Wang Xing Wu Peng Zhou David Wei Zhang Chenjian Wu Wenzhong Bao State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai200433China In Situ Devices Center Shanghai Key Laboratory of Multidimensional Information ProcessingEast China Normal UniversityShanghai 200241China School of Electronic Information Soochow UniversitySuzhou215006China

The investigation of two-dimensional(2D)materials has advanced into practical device applications,such as cascaded logic ***,incompatible electrical properties and inappropriate logic levels remain enormous *** this work,a doping-free strategy is investigated by top gated(TG)MoS_(2) field-effect transistors(FETs)using various metal gates(Au,Cu,Ag,and Al).These metals with different work functions provide a convenient tuning knob for controlling threshold voltage(V_(th))for MoS_(2) *** instance,the Al electrode can create an extra electron doping(n-doping)behavior in the MoS_(2) TG-FETs due to a dipole effect at the gate-dielectric *** this work,by achieving matched electrical properties for the load transistor and the driver transistor in an inverter circuit,we successfully demonstrate wafer-scale MoS_(2) inverter arrays with an optimized inverter switching threshold voltage(V_(M))of 1.5 V and a DC voltage gain of 27 at a supply voltage(V_(DD))of 3 *** work offers a novel scheme for the fabrication of fully integrated multistage logic circuits based on wafer-scale MoS_(2) film.

关键词： Two-dimensional semiconductor MoS_(2) Top gate Field effect transistor Logic inverter

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A 12.87-dB Gain 10.5-dBm OPldB60-to-66-GHz LNA in 0.15-μm GaAs pHEMT Technology

A 12.87-dB Gain 10.5-dBm OPldB60-to-66-GHz LNA in 0.15-μm G...

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2022 IEEE the Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2022

作者： Li, Xuefeng Wang, Yuting Wu, Tianxiang Chen, Yong Ren, Junyan Ma, Shunli School of Microelectronics Fudan University State Key Laboratory of ASIC and System Shanghai China State Key Laboratory of ASIC and System School of Information Science and Technology Fudan University Shanghai China University of Macau State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST Macao China

ISBN: (纸本)9781665450690

This paper presents a V-band low noise amplifier (LNA) implemented in a 0.15-μm Gallium Arsenide (GaAs) pseudomorphic high electron-mobility transistor (pHEMT) technology. The LNA adopts a three-stage common-source (CS) topology. Each transistor has a bias circuit, and the microstrip-line inductor is used to realize the input noise matching network, the interstage, and the output matching network. Circuit simulations show that our LNA scores a 12.87-dB small-signal gain, the 3-dB bandwidth ranges from 60 GHz to 66 GHz, and the current consumption is 30 mA under a 5-V supply voltage. Its noise figure is 5.9 dB, and the output 1-dB compression point is 10.5 dBm. The chip area is 1.32× 1.5mm2. © 2022 IEEE.

关键词： Low noise amplifiers

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Suppression of Back-Gating Effect by Integrated Substrate Termination Network for 200V Monolithic GaN Half-Bridge Power IC 17

Suppression of Back-Gating Effect by Integrated Substrate Te...

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17th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2024

作者： Zhao, Mengyao Zheng, Yifei Ma, Yanfeng Sun, Yuan Wang, Denggui Pan, Chuanqi Zhou, Jianjun Li, Sheng Zhang, Long Liu, Siyang Sun, Weifeng National ASIC System Engineering Research Center School of Integrated Circuits Southeast University Jiangsu Nanjing China National Key Laboratory of Solid-State Microwave Devices and Circuits Jiangsu Nanjing China

ISBN: (纸本)9798350361834

We fabricate a 200V monolithic GaN half-bridge power IC featuring an integrated substrate termination network (ISTN). The ISTN utilizes two-dimensional electron gas resistors to dynamically control the substrate potential so that detrimental back-gating effects and dynamic on-resistance ( R o n ) degradation is effectively suppressed. The proposed GaN power IC scheme with ISTN demonstrates remarkable performance by minimizing the increase in dynamic R o n for both the high-side and low-side HEMT at power supply of 200V, respectively. The fabricated monolithic ISTN can minimize parasitic elements compared with the board-level substrate termination network in previous work, while no additional process complexity is required. © 2024 IEEE.

关键词： Gallium nitride

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HRPoseFormer: High-Resolution Transformer for Human Pose Estimation via Multi-Scale Token Aggregation 16

HRPoseFormer: High-Resolution Transformer for Human Pose Est...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Yu, Xiao-Wei Chen, Geng-Sheng Fudan University State Key Laboratory of Asic and System No.825 Zhangheng Road Shanghai201203 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Vision Transformer has a promising application in human pose estimation (HPE). However, due to the use of similar receptive fields of the tokens, existing Transformers are still lacking the ability of dealing with the scale variance. In this paper, we propose a High-Resolution Transformer-based network - HRPoseFormer for HPE. First, we bring in a self-attention module to the parallel multi-resolution structure for a more effective capture of the multi-scale features with lower computing complexity. Second, we utilize detail-specific feed-forward layers to supplement more elaborate local features to the Transformer blocks. Third, we leverage the unbiased data processing (UDP) strategy to help acquire a more accurate transformation between the different coordinate systems and the keypoint formats. Experiments show that the new HRPoseFormer model surpasses the existing state-of-the-art methods with a superior performance of 77.0 AP on the COCO keypoint dataset. © 2022 IEEE.

关键词： Metadata

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Stacking monolayers at will:A scalable device optimization strategy for two-dimensional semiconductors

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Nano Research 2022年第7期15卷 6620-6627页

作者： Xiaojiao Guo Honglei Chen Jihong Bian Fuyou Liao Jingyi Ma Simeng Zhang Xinzhi Zhang Junqiang Zhu Chen Luo Zijian Zhang Lingyi Zong Yin Xia Chuming Sheng Zihan Xu Saifei Gou Xinyu Wang Peng Gong Liwei Liu Xixi Jiang Zhenghua An Chunxiao Cong Zhijun Qiu Xing Wu Peng Zhou Xinyu Chen Ling Tong Wenzhong Bao State Key Laboratory of ASIC and System School of MicroelectronicsZhangjiang Fudan International Innovation CenterFudan UniversityShanghai 200433China The Hong Kong Polytechnic University Shenzhen Research Institute Shenzhen 518057China Department of Physics State Key Laboratory of Surface PhysicsInstitute of Nanoelectronic Devices and Quantum Computing and Key Laboratory of MicroFudan UniversityShanghai 200433China State Key Laboratory of ASIC and System School of Information Science and EngineeringFudan UniversityShanghai 200433China Shanghai Key Laboratory of Multidimensional Information Processing Department of Electronic Engineering East China Normal UniversityShanghai 200241China Shenzhen Six Carbon Technology Shenzhen 518055China Department of Chemistry and Shanghai Key Laboratory of Molecular Catalysis and Innovative Materials Fudan UniversityShanghai 200433China

In comparison to monolayer(1L),multilayer(ML)two-dimensional(2D)semiconducting transition metal dichalcogenides(TMDs)exhibit more application potential for electronic and optoelectronic devices due to their improved current carrying capability,higher mobility,and broader spectral ***,the investigation of devices based on wafer-scale ML-TMDs is still restricted by the synthesis of uniform and high-quality ML *** this work,we propose a strategy of stacking MoS_(2) monolayers via a vacuum transfer method,by which one could obtain wafer-scale high-quality MoS_(2) films with the desired number of layers at *** optical characteristics of these stacked ML-MoS_(2) films(>2L)indicate a weak interlayer *** stacked MLMoS_(2) phototransistors show improved optoelectrical performances and a broader spectral response(approximately 300-1,000 nm)than that of 1L-MoS_(2).Additionally,the dual-gate ML-MoS_(2) transistors enable enhanced electrostatic control over the stacked ML-MoS_(2) channel,and the 3L and 4L thicknesses exhibit the optimal device performances according to the turning point of the current on/off ratio and the subthreshold swing.

关键词： two-dimensional semiconductor field-effect transistors chemical vapor deposition(CVD)synthesis interlayer coupling vacuum transfer method dual-gate transistor

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Improving Topology Consistency of Retinal Vessel Segmentation via a Double U-Net with Asymmetric Convolution

Improving Topology Consistency of Retinal Vessel Segmentatio...

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International Conference on Medical Imaging and Computer-Aided Diagnosis, MICAD 2021

作者： Li, Xiaomin Chen, Gengsheng State Key Laboratory of ASIC and System Fudan University No. 825 Zhangheng Road Shanghai201203 China

ISBN: (纸本)9789811638794

Retinal vessel segmentation (RVS) plays a significant role in the diagnosis of ocular diseases, like diabetic retinopathy and glaucoma disease. However, many works have neglected keeping the topology consistency of the vascular segmentation, which is more crucial for the clinical diagnosis system. In this paper, we propose a double U-shape network to tackle this problem. The first U-Net architecture is DAS-UNet. With the help of the dense connectivity and the parallel atrous convolution (PAC) block, DAS-UNet can exploit various receptive fields to segment retinal vessel accurately. Through salient computing block (SCB), it can focus more on responsive regions and suppress uncorrelated regions. In addition, we add an auxiliary U-Net which adopts asymmetric convolutions to strengthen the kernel skeleton and correct the connectivity incoherence of retinal vessels. By exploiting the weighted Binary Cross Entropy loss (BCE loss), the double U-shape network can segment retinal vessels more accurately and improve the topological consistency of the segmented vessels. We tested the proposed network for accurate RVS task on DRIVE benchmark, which achieved the SOTA performance with a better segmentation results in terms of topology. © 2022, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Topology

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A Reusable AI acceleration Architecture based on Matrix Multiplication for Convolutional Neural Network with Digital Signal ProcessingTasks 15

A Reusable AI acceleration Architecture based on Matrix Mult...

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15th IEEE International Conference on asic, asicON 2023

作者： Chen, Bisheng Li, Xiayu Lu, Jicheng Yu, Jun Fudan University State Key Laboratory of ASIC and System Shanghai200433 China Shanghai Fudan Microelectronics Group Co. Ltd Shanghai200000 China

ISBN: (纸本)9798350312980

As AI begins to face more complex application scenarios, such as intelligent radar, autopilot and intelligent 5G, it often needs to work together with other traditional algorithms, mainly Digital Signal Processing (DSP) algorithms now. The proposed heterogeneous architecture with an AI core (on asic, for CNN) and IP core (on FPGA, for DSP) is usually adopted, but that's inefficient due to the inconsistency in data transmission and operating frequency between chips. In order to solve this problem, this paper has proposed a reusable architecture based on Matrix Multiplication, which supports convolution, FFT and FIR operations on asic. We first analyzed the relationship among Convolution, FFT and FIR and find the best reusable architecture is Matrix multiplication. Then we decomposed the Convolution, FFT and FIR into Matrix multiplication, and designed the hardware architecture for them. Finally, we used Image registration algorithm to test the performance of our architecture, and get 500% speed up. © 2023 IEEE.

关键词： AI Acceleration Fast Fourier Transform (FFT) Finite Impulse Response (FIR) Reusable Architecture

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A High-Throughput Luma Mapping with Chroma Scaling Decoder for Versatile Video Coding 15

A High-Throughput Luma Mapping with Chroma Scaling Decoder f...

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15th IEEE International Conference on asic, asicON 2023

作者： He, Zekai Li, Wei Huang, Leilei Fan, Yibo Fudan University State Key Laboratory of ASIC and System Shanghai200433 China East China Normal University Institute of Microelectronic Circuits and Systems Shanghai200241 China

ISBN: (纸本)9798350312980

As a new coding tool of Versatile Video Coding, Luma Mapping with Chroma Scaling (LMCS) maps luma samples and scales chroma residuals based on the mapping function to improve video quality and compression ratio. To achieve real-time decoding and improve the throughput, a hardware decoder needs to be developed. In this paper, a high throughput LMCS hardware decoder design was proposed. Three separate modules were designed to realize the LMCS processes with two implementation schemes of the Luma Mapping module discussed and the better one used. The proposed design reached 535 MHz at 28nm technology, capable of processing videos at 4K@120fps. © 2023 IEEE.

关键词： hardware design in-loop filter luma mapping with chroma scaling Versatile Video Coding video coding

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