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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Chen, Yingxin Wang, Haihua Wan, Jing Fudan University State Key Laboratory of Asic and System School of Information Science and Technology Shanghai200433 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

In this work, we demonstrate Z2-FET (zero subthreshold swing and zero impact ionization FET) and UJ-FET (unijunction FET) on silicon-on-insulator substrate utilizing a CMOS-compatible process. Attributed to novel positive feedback mechanisms, the devices can break the subthreshold swing (SS) limitation in conventional MOSFET and exhibit sharp-switching characteristics. Based on the positive feedback between carrier flow and band modulation, the fabricated Z2-FET has been demonstrated with SS of 14.2 mV/dec and ION/IOFF ratio of 1.5×107. Based on the positive feedback between junction voltage and carrier injection, the fabricated UJ-FET has been demonstrated with SS of 1.5 mV/dec and ION/IOFF ratio of 3.4×107. © 2022 IEEE.

关键词： Impact ionization

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2T1C DRAM based on semiconducting MoS_(2) and semimetallic graphene for in-memory computing

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National Science Open 2023年第4期2卷 65-75页

作者： Saifei Gou Yin Wang Xiangqi Dong Zihan Xu Xinyu Wang Qicheng Sun Yufeng Xie Peng Zhou Wenzhong Bao State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityZhangjiang Fudan International Innovation CenterShanghai 200433China Shenzhen Six Carbon Technology Shenzhen 518055China

In-memory computing is an alternative method to effectively accelerate the massive data-computing tasks of artificial intelligence(AI)and break the memory *** this work,we propose a 2T1C DRAM structure for in-memory *** integrates a monolayer graphene transistor,a monolayer MoS_(2)transistor,and a capacitor in a two-transistor-onecapacitor(2T1C)*** this structure,the storage node is in a similar position to that of one-transistor-one-capacitor(1T1C)dynamic random-access memory(DRAM),while an additional graphene transistor is used to accomplish the nondestructive readout of the stored ***,the ultralow leakage current of the MoS_(2)transistor enables the storage of multi-level voltages on the capacitor with a long retention *** stored charges can effectually tune the channel conductance of the graphene transistor due to its excellent linearity so that linear analog multiplication can be *** of the almost unlimited cycling endurance of DRAM,our 2T1C DRAM has great potential for in situ training and recognition,which can significantly improve the recognition accuracy of neural networks.

关键词： molybdenum disulfide(MoS_(2)) graphene DRAM in-memory computing

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A 250MS/s, 12 Bit Pipeline-SAR ADC Using Coarse-Fine Ring Amplifier

A 250MS/s, 12 Bit Pipeline-SAR ADC Using Coarse-Fine Ring Am...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Linghao Liu Junyan Ren Fan Ye Department of Microelectronics State Key Laboratory of ASIC and System Fudan University Shanghai China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

The ring amplifier is an energy effective choice for high performance pipeline ADC. However, sensitivity to process, supply voltage and temperature (PVT) variations and complex stability mechanism make it less practical. This brief introduces a coarse-fine ring amplifier (CFRingAmp) that allows individual designs of large-signal and small-signal processes. With a large and a smaller dead-zones switched by the self-detect-and-switch block, both stability and accuracy are well designed over corners. Furthermore, a 250MS/s, 12-bit pipeline-SAR ADC is implemented adopting the proposed CFRingAmp. Simulated in 28nm CMOS, the ADC achieves an SNDR of 64.1 dB and an SFDR of 74.9 dB over corners at Nyquist frequency while consuming 4.5mW, resulting a Walden figure-of merit (FoM) of 12.7 fJ/conversion step.

关键词： Temperature sensors Accuracy Sensitivity Simulation Voltage Switches Stability analysis Circuit stability Registers Thermal stability

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SFFTNet: Sparse Feature Fusion Transformer Network for Image Deblurring

SFFTNet: Sparse Feature Fusion Transformer Network for Image...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Faxing Lei Chao Liu Wei Li Minge Jing Xiankui Xiong Xuanpeng Zhu Yibo Fan State Key Laboratory of ASIC and System Fudan University China ZTE Corporation China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

The U-Net structure, with its an encoder-decoder architecture, has been widely adopted by many deep learning methods for image deblurring. Most methods concentrate on the design of encoder and decoder block and use skip connections to connect them. However, this simple skip connection strategy is insufficient to fully exploit the correlation of multi-scale features, which can result in a potential loss of deblurring performance. To address this issue, we design an effective Sparse Feature Fusion Transformer capable of integrating multi-scale features to replace the skip connections in the U-Net framework. Specifically, We propose a cross-attention mechanism with a learnable top-k selection operator to adaptively preserve highly correlated cross-attention values for feature fusion. This approach ensures that the fused multi-scale features effectively integrate contextual information, resulting in high-quality image deblurring. Additionally, we introduce the position encoding generator scheme to ensure that our deblurring network can be applied to images of any size. Comprehensive experimental results demonstrate that our proposed method outperforms the the state-of-the-art methods.

关键词： Deep learning Image coding Correlation Fuses Filtering Transformers Generators

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TENG: A General-Purpose and Efficient Processor Architecture for Accelerating DNN

TENG: A General-Purpose and Efficient Processor Architecture...

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IEEE International Conference on Artificial Intelligence Circuits and systems (AICAS)

作者： Zekun Zhang Yujie Cai Tianjiao Liao Chengyu Xu Xin Jiao State Key Laboratory of ASIC and System Fudan University Shanghai China SenseTime Research

ISBN: (数字)9798350383638

ISBN: (纸本)9798350383645

Deep learning has been widely deployed in the fields such as computer vision and speech, etc. However, with the development of deep learning algorithms, neural networks have gradually become more complex, the subsequent computing requirements for huge amounts of data have posed greater challenges to hardware updates and improvements. In this work, a general-purpose and efficient deep neural network (DNN) accelerator is proposed, named TENG. In TENG, we proposed a unified architecture with general and dedicated coexistence to support various network operators, and the memory access engine in TENG optimizes off-chip data transmission to achieve better bandwidth utilization. The correctness of TENG is verified on FPGA and implemented in 7-nm FinFET technology. It achieves 4TOPS peak throughput@INT16 and has an energy efficiency of 5.15TOPS/W using VGG-16 at 1GHz clock frequency.

关键词： Deep learning Spectral efficiency system performance Memory management Artificial neural networks Bandwidth Throughput

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Impact Analysis of Negative Gate Voltage on SiCMOS Reliability Under OFF-state Avalanche Stress

Impact Analysis of Negative Gate Voltage on SiCMOS Reliabili...

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International Symposium on Physical & Failure Analysis of Integrated Circuits

作者： Hang Xu Jianbin Guo Tianyang Feng Yafen Yang Qing-Qing Sun David Wei Zhang State Key Laboratory of ASIC and System School of Microelectronics Fudan University Shanghai China

ISBN: (数字)9798350360608

ISBN: (纸本)9798350360615

This paper fully researches and analyzes the effect of negative OFF-state gate-source bias voltage (V GS , off) on the device degradation under OFF-state avalanche stress. It is found that the degradation associated with negative V GS ,off is much greater than that of 0V V GS ,off and negative bias temperature instability (NBTI). While the shift in threshold voltage (V T ) and on-resistance (R on ) are relatively small, and the biggest change is reverse leakage current (I Dss ) corresponds to the generation of interface state. This phenomenon is analyzed in conjunction with Technology Computer Aided Design (TCAD) analysis, which demonstrate that under the avalanche stress condition, the electric field at the bottom of the gate oxide attains substantial magnitudes. Moreover, the introduction of negative V GS ,off significantly amplifies the electric field in this region, which has a significant impact on the long-term reliability of the device.

关键词： Degradation Negative bias temperature instability Manufacturing processes Thermal variables control Logic gates Reliability engineering Threshold voltage

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Confidence Judgement Network: An Efficient Sample Filter for Lifelong Distillation 16

Confidence Judgement Network: An Efficient Sample Filter for...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Zhang, Zhenyin Xue, Yue Chen, Gengsheng Fudan University State Key Laboratory of Asic and System No.825 Zhangheng Road Shanghai201203 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Unlabeled raw data of the real world collected by the edge computing platforms can be utilized to improve the performance of the lightweight deep learning models by using Lifelong Distillation (LD) method. However, not all the raw data samples are equally beneficial to such a process. In this paper, we propose a novel Confidence Judgement Network (CJN) to refine the raw data and to accelerate the LD processing. First, we design a new CJN model and use it to filter easy samples. Second, we scissor Lite-HRNet to get a slimmed student network - Half-LiteHRNet for knowledge distillation. Finally, we apply the new LD+CJN method to train our new image segmentation network, receiving a 39.4% reduction in network size and a 17.1% reduction in calculation load. Experiments show that, the new CJN model successfully improves LD by a roughly +3.96% increase in AP with a tiny cost, a negligible 0.038% rise in calculation load. © 2022 IEEE.

关键词： Semantic Segmentation

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A Feature Map Lossless Compression Framework for Convolutional Neural Network Accelerators

A Feature Map Lossless Compression Framework for Convolution...

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IEEE International Conference on Artificial Intelligence Circuits and systems (AICAS)

作者： Zekun Zhang Xin Jiao Chengyu Xu State Key Laboratory of ASIC and System Fudan University Shanghai China SenseTime Research

ISBN: (数字)9798350383638

ISBN: (纸本)9798350383645

This paper proposes a predictor-based lossless compression algorithm for the feature maps present within convolutional neural networks (CNNs), which provides the possibility to solve the system bandwidth bottleneck and excessive power consumption problem of hardware acceleration. It is also an algorithm-hardware co-design methodology, yielding a hardware-friendly compression approach with low power consumption. The performance of the algorithm is evaluated in the detection, recognition, and segment CNN tasks respectively. Results show that an average compression ratio of 3.03x and a gain of nearly 50% over existing methods can be achieved for VGG-16; 2.78x and a gain of around 51% for ResNet-18; 2.45 and a gain of nearly 38% for SegNet.

关键词： Power demand Circuits and systems Fitting Bandwidth Prediction algorithms Convolutional neural networks Task analysis

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A Dynamic-Texture-Guided Fast Algorithm for Geometric Partitioning Mode of VVC 15

A Dynamic-Texture-Guided Fast Algorithm for Geometric Partit...

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15th IEEE International Conference on asic, asicON 2023

作者： Yang, Xuehang Li, Wei Chen, Shushi Huang, Leilei Fan, Yibo Fudan University State Key Laboratory of ASIC & System Shanghai200433 China East China Normal University Institute of Microelectronic Circuits and Systems Shanghai200241 China

ISBN: (纸本)9798350312980

Geometric Partitioning Mode (GPM) efficiently describes the irregular edges of motion fields, but it has high computational complexity. To address this issue, many fast algorithms directly detect edges based on static textures. However, those algorithms usually lead to performance loss due to the absence of motion information. Given the situation, this paper proposes a new dynamic-texture-guided fast algorithm, which detects edges based on both dynamic textures and static textures. To reduce the complexity, partitioning modes to be tested for GPM are selectively filtered based on the edges detected. To reduce the encoding time, GPM process is skipped when no edges exist. Experimental results show that it reduces GPM encoding time by 13.79% with just a 0.15% BD-rate loss compared to the Versatile Video Coding (VVC) reference software VTM-16.0, demonstrating better coding performance than existing fast algorithms. © 2023 IEEE.

关键词： geometric partitioning mode histogram texture versatile video coding

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The development of transfer technologies for advanced 2D circuits integration

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Information & Functional Materials 2024年第3期1卷 304-322页

作者： Zhenggang Cai Liwei Liu Peng Zhou State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghaiChina Frontier Institute of Chip and System Fudan UniversityShanghaiChina

In the light of the scaling limitations of conventional CMOS technology,twodimensional(2D)materials offer a transformative avenue for advancing Moore's law in the post‐Moore *** technology for transferring 2D materials serves as a crucial link between their synthesis and device *** review provides a comprehensive assessment of advancements in the transfer technologies and integration of 2D materials,which are essential for next‐generation ***,state‐of‐the‐art methodologies for highquality,wafer‐scale transfer of 2D materials,including both wet and dry transfer methods are thoroughly *** the requirements for massive transfer of 2D materials compatible with silicon line while preserving their intrinsic properties are ***,we focus on 2D integration techniques,paying special attention to the construction of van der Waals contacts at the 2D material/dielectric interface and 2D material/metal electrode ***,the potential for layer‐by‐layer or tier‐by‐tier transfer 2D devices for monolithic 3D integration was also *** review concludes by highlighting the significant challenges that remain in leveraging the potential of 2D materials at the circuit and system levels,proposing forward‐looking development in transfer strategies.

关键词： monolithic 3D integration transfer of 2D materials transfer of gate dielectrics transfer of metal electrodes

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