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IEEE International Conference on Circuits and systems (ICCS)

作者： Daiyu Zhang Ting Yi State Key Laboratory of ASIC and System Fudan University Shanghai China

Capacitive sensors are one of the most widely used sensors today. In recent years, High resolution has assumed a paramount role in sensor design, guaranteeing precise measurement outcomes. Quantification to the aF level is urgently needed. This paper presents the first dynamic Zoom capacitance to digital converter (CDC) incorporating noise coupling (NC) technology, which is intended for high-precision sensor applications in the audio domain. The proposed dynamic CDC is a hybrid of a high-resolution $\mathbf{\Delta}\mathbf{\Sigma}$ modulator $(\mathbf{\Delta}\mathbf{\Sigma}\mathbf{M})$ and a high-efficiency SAR-based CDC to achieve better performance. It is implemented in the TSMC 180 nm process, and the simulation results show that it achieves 109.9dB DR and 109.3dB SNR within the bandwidth of 20kHz, consuming $\mathbf{81}\boldsymbol{\mu}\mathbf{W}$ from a 1.2V supply. These advancements are accomplished through the combined utilization of coarse and fine conversions, noise coupling techniques, SAR-assisted multi-bit quantizers, and operational transconductance amplifiers (OTAs) based on dynamic bias inverters.

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A 12.1-16.5GHz Resistance Self-biased Inverse Class-F23 VCO Achieving 20-54kHz 1/f3 Corner Frequency

A 12.1-16.5GHz Resistance Self-biased Inverse Class-F23 VCO ...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Jiayu Jing Wei Li Ren Yuan Hongtao Xu State Key Laboratory of ASIC & System Fudan University Shanghai China

This paper presents a resistance self-biased inverse class-F 23 voltage-controlled oscillator (VCO). The VCO keeps ultra-low amplitude and phase mismatches by inducing a resistance between primary and secondary coils of the transformer. It also induces both 2 nd and 3 rd harmonic resonances to reduce 1/f 3 corner frequency. The VCO is designed in 40nm CMOS with frequency range of 12.1GHz to 16.5GHz. The post simulation results show that it achieves − 118dBc/Hz and −109dBc/Hz at 1MHz offset frequency at 12.1GHz and 16.5GHz respectively, whose 1/f 3 corner frequency is 54kHz and 20kHz. The power consumption of the VCO is 14.3mW at 1.1V supply. The core area is 0.03mm 2 .

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High-Performance Placement Engine for Modern Large-Scale FPGAs with Heterogeneity and Clock Constraints

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems 2024年第3期43卷 956-969页

作者： Zhu, Ziran Mei, Yangjie Deng, Kangkang He, Huan Chen, Jianli Yang, Jun Chang, Yao-Wen Southeast University National ASIC System Engineering Research Center School of Integrated Circuits Nanjing210096 China Peking University Beijing International Center for Mathematical Research Beijing100871 China Hangzhou Huawei Enterprises Telecommunication Technologies Company Ltd. Central Hardware Planning & Architecture Design Department Hangzhou310000 China Fudan University State Key Laboratory of ASIC and System Shanghai200433 China National Taiwan University Graduate Institute of Electronics Engineering The Department of Electrical Engineering Taipei10617 Taiwan

As field-programmable gate array (FPGA) architectures continue to evolve and become more complex, the heterogeneity and clock constraints imposed by modern FPGAs have posed significant challenges to FPGA placement. This article proposes a high-performance placement engine for modern large-scale FPGAs with heterogeneity and clock constraints. To improve efficiency and scalability, we develop a clustering method considering both internal/external connectivity and the balance of block types to build the hierarchy. In each hierarchy level, we propose a hybrid penalty and augmented Lagrangian method (HPALM) to convert the FPGA global placement with heterogeneity and clock constraints into a series of unconstrained optimization subproblems, then use the Adam method to solve each subproblem. In particular, we prove that the HPALM is globally convergent for global placement. Besides, a matching-based IP block legalization is developed to legalize the DSPs and RAMs, and a multistage packing is presented to cluster LUTs and FFs into HCLBs. Finally, we propose a history-based legalization to legalize CLBs in an FPGA, and a simulated-annealing-based detailed placement is presented to reduce the wirelength while maintaining legality. Compared with the state-of-the-art works, experimental results based on the ISPD 2017 contest benchmarks show that the proposed algorithm can achieve the shortest routed wirelength in a reasonable runtime. © 1982-2012 IEEE.

关键词： Table lookup

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LEAN: Local-Enhanced Attention Network for Bad Weather Image Restoration 16

LEAN: Local-Enhanced Attention Network for Bad Weather Image...

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Ying, Han-Qian Li, Xiao-Min Xu, Wei Fudan University State Key Laboratory of Asic and System Shanghai201203 China Co. Ltd Shanghai201203 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Bad weather image restoration is an important pre-processing task for many vision applications. Seeking a remarkable performance, existing works select to place their focus on one specific degradation, lacking the ability to cope with various weather conditions simultaneously. In this paper, we propose a local-enhanced attention network (LEAN) for restoring images with multiple weather degradations. First, we initiatively bring in cross-level transformer blocks to the encoder-decoder structure for a more effective utilization of the multi-scale features. Second, we design a local-enhanced self-attention (LESA) mechanism using a residual convolutional projection to reserve richer original information for subsequent feature reconstruction. Third, we bond smooth-L1 loss, frequency loss and perceptual loss together to accelerate the training. Experiment results show that LEAN has surpassed all the existing peering works in PSNR, increasing 2.06% on OutdoorRain-Test1, 3.04% on Snow100K-L and 3.36% on Raindrop-TestA, respectively and simultaneously. © 2022 IEEE.

关键词： Image reconstruction

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Multi-objective Design Space Exploration for High-Level Synthesis via Bayesian Optimization

Multi-objective Design Space Exploration for High-Level Synt...

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Electronics Design Automation (ISEDA), International Symposium of

作者： Huizhen Kuang Lingli Wang State Key Laboratory of ASIC and System Fudan University Shanghai China

High-level Synthesis (HLS) becomes popular since it can improve productivity of circuit designs. The optimization of HLS is necessary since the design space is vast and different configurations can lead to various power, performance and area (PPA). In this paper, we model the design space exploration (DSE) as a multi-objective black-box optimization problem via Bayesian optimization with float encoding method to explore the Pareto front of HLS designs for PPA objectives, where Multi-objective Tree-structured Parzen Estimator (MOTPE) is adopted as the surrogate model which can search the tree-structured design space efficiently and Expected Hypervolume Improvement (EHVI) is used as the acquisition function to guide the optimization. The experimental results show that our method achieves LPDA gains by 66.30% and 41.25%, compared with two meta-heuristic algorithms, simulated annealing (SA) and NSGA-II. Our learned Pareto front is closer to the reference Pareto front than SA and NSGA-II, with an average improvement in ADRS by 94.72% and 69.58% respectively.

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Explore the Feedback Interconnects in Intra-Cluster Routing for FPGAs

Explore the Feedback Interconnects in Intra-Cluster Routing ...

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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Kaichuang Shi Hao Zhou Lingli Wang State Key Laboratory of ASIC and System Fudan University Shanghai China

Routing architecture has a significant effect on the performance and area of FPGA. In academia, the global routing architecture is mainly based on the connection blocks (CBs) and switch blocks (SBs). There are input crossbars inside the logic blocks (LBs) which are used to connect the LB pins and feedbacks to the LUT inputs. Muxes in the crossbar are used to implement the intra-cluster connections. In the previous researches, there are few papers focusing on the exploration of feedback interconnects. Besides, it is hard to model the complex feedback interconnects in commercial FPGAs as the feedbacks can only connect to the muxes in the crossbar in the CB-SB architecture. In this paper, we enhance VPR to support GRB (general routing block) architecture which replaces the CBs, SBs and input crossbars to alleviate this problem and explore complex feedback interconnects. Four parameters are proposed to describe the feedback interconnects architecture. Compared to the CB-SB like feedback interconnects architecture, experimental results show that the proposed architecture can achieve 4.5% improvement on the routing area, 2.1% improvement on the critical path delay and 6.5% improvement on the area-delay product with VTR benchmarks.

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A CFET Unit Cell based MUX21 design strategy 16

A CFET Unit Cell based MUX21 design strategy

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Zhu, Xiao-Na Wei, Chen-Cheng Ding, Rong-Zheng Yu, Shao-Feng Fudan University State Key Laboratory of Asic and System School of Microelectronics Shanghai200433 China Jiashan Fudan Institute China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

With the Moore's law approaching ultimate limitation, device structure has been revolutionary changing, from FinFET to GAA FET, and then a new semiconductor device structure, CFET, has been regarded the continuing structure after GAA. CFET has significant area miniaturization advantages, but its folding N/PFET vertically brings new difficulties in process flow and new strategies for design enablement like in standard cell library. In this paper, we proposed the design consideration priority in CFET unit cell constructed standard cell library, and give examples like MUX21in obeying our rule. Two different schematics of MUX21 are designed at multiple levels: process flow, layout, and circuit performance. The proposed rule in CFET unit cell for standard library cell and the specific DTCO flow in this MUX21 circuit can provide the pathway for other circuit designs of standard cell library composed of CFET unit cell. © 2022 IEEE.

关键词： Cytology

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Electronics based on two-dimensional materials:Status and outlook

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Nano Research 2021年第6期14卷 1752-1767页

作者： Senfeng Zeng Zhaowu Tang Chunsen Liu Peng Zhou State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghai200433China School of Computer Science Fudan UniversityShanghai200433China

Since Moore’s law in the traditional semiconductor industry is facing shocks,More Moore and More than Moore are proposed as two paths to maintain the development of the semiconductor industry by adopting new architectures or new materials,in which the former is committed to the continued scaling of transistors for performance enhancement,and the latter pursues the realization of functional diversification of electronic ***-dimensional(2D)materials are supposed to play an important role in these two *** More Moore,the ultimate thin thickness and the dangling-bond-free surface of 2D channels offer excellent gate electrostatics while avoiding the degradation of carrier mobility at the same time,so that the transistors can be further scaled down for higher *** More than Moore,devices based on 2D materials can well meet the requirements of electronic systems for functional diversity,like that they can operate at high frequency,exhibit excellent sensitivity to the changes in the surroundings at room temperature,have good mechanical flexibility,and so *** this review,we present the application of 2D materials in More Moore and More than Moore domains of electronics,outlining their potential as a technological option for logic electronics,memory electronics,radio-frequency electronics,sensing electronics,and flexible electronics.

关键词： More Moore More Than Moore two-dimensional materials transition metal dichalcogenides(TMDs)

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A Low-Complexity Algorithm for JPEG-LS-Based RAW Domain Compression

A Low-Complexity Algorithm for JPEG-LS-Based RAW Domain Comp...

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International Conference on asic

作者： Yeping Zheng Tingting Li Wei Li Faxing Lei Jiarui Liu Yibo Fan State Key Laboratory of ASIC & System Fudan University Shanghai China

In this paper, a novel lossless and near-lossless RAW image compression algorithm based on JPEG-LS is proposed. To achieve high performance and low complexity, the algorithm reduce the context module, merge the run mode with the regular mode and propose an adaptive Golomb-Rice coding technique. The algorithm mainly consists of four parts : pixel structure conversion, pixel prediction, run mode module and adaptive Golomb-Rice coding module. Compared to JPEG-LS, this algorithm achieves comparable performance to JPEG-LS while reducing complexity. Additionally, it allows users to adjust parameters to achieve lossless and near-lossless compression supporting random access and non-random access.

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VIB: A Versatile Interconnection Block for FPGA Routing Architecture

VIB: A Versatile Interconnection Block for FPGA Routing Arch...

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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Kaichuang Shi Hao Zhou Lingli Wang State Key Laboratory of ASIC and System Fudan University Shanghai China

Routing architecture has a large impact on the FPGA performance and area. In academia, the routing architecture is mainly based on the connection blocks (CBs) and switch blocks (SBs). There are also input crossbars inside the logic blocks (LBs). Muxes with high fanins are used to implement the intra- and inter-cluster connections. In the previous researches, CBs, SBs and input crossbars are designed separately which may miss some potential optimization spaces to trade off area, delay and routability. Besides, it is hard to model the complex routing architecture in commercial FPGAs. In this paper, we propose a novel tile-based routing architecture, versatile interconnection block (VIB) which replaces the CBs, SBs and input crossbars to alleviate this problem. All the routing resources are included in the VIBs which are based on two level mux topology used in many commercial FPGAs. Six parameters are proposed to describe the VIB architecture. In addition, VTR 8 is enhanced to support the proposed VIB architecture. Then, we compare the proposed architecture with the latest work of two level mux design. Experimental results show that the proposed VIB architecture can achieve 18.9% improvement on the routing area, 2% improvement on the routability and 16.6% improvement on the area-delay product with VTR benchmarks.

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