In this paper, a Frequency domain Fast Wavelet Collocation Method (FFWCM) is proposed for the simulation of high-speed linear VLSI circuits. Compared with the time domain Fast Wavelet Collocation Method, the proposed ...
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ISBN:
(纸本)0780374487
In this paper, a Frequency domain Fast Wavelet Collocation Method (FFWCM) is proposed for the simulation of high-speed linear VLSI circuits. Compared with the time domain Fast Wavelet Collocation Method, the proposed FFWCM solves the state equation in the frequency domain and reduces the problem unknowns by avoiding expanding all the state variables with wavelet functions. Moreover, frequency domain singularities can be easily handled by an efficient adaptive scheme and the simulation error bound is guaranteed in the frequency domain. As a result, memory space and simulation time are greatly reduced by FFWCM, which makes it efficient for simulating large scale circuits. Numerical experimental results have further demonstrated the promising features of FFWCM.
In this paper, we propose a fast wavelet collocation algorithm for high-speed clock tree simulation. Taking advantage of the specific structure of clock trees and the superior computational property of wavelets, the p...
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ISBN:
(纸本)0780374487
In this paper, we propose a fast wavelet collocation algorithm for high-speed clock tree simulation. Taking advantage of the specific structure of clock trees and the superior computational property of wavelets, the proposed algorithm presents the following merits. (1) It can perform both transient simulation and steady-state analysis with arbitrary input. (2) It employs nonlinear buffer model and nonuniform interconnect wire model. (3) It has a low computational complexity O(N) and can deal with considerably large circuits. (4) The proposed wavelet method works in time domain so that the simulation error in time domain can be well-controlled. Numerical experiment results demonstrate the promising features of the proposed algorithm in high-speed clock tree simulations.
A, novel MEMS gas sensor including a PZT thin film layer and a zeolite layer is developed in this paper, which shows effective combination of high sensitivity and high selectivity. Working in resonating mode, the sens...
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A, novel MEMS gas sensor including a PZT thin film layer and a zeolite layer is developed in this paper, which shows effective combination of high sensitivity and high selectivity. Working in resonating mode, the sensor depicts the mass loading due to molecular adsorption of the zeolite by the frequency shift. The relationship between the frequency shift in percent and the concentration of Freon is linear. The minimum mass loading of 3.5 /spl times/ 10/sup -9/ and the sensitivity of -0.0024%/ppm can be determined from the experimental results.
A novel controlled slew-rate (CSR)output driver is presented to reduce the simultane-ous switching noise (SSN). The SSN effects on digitalcircuits and the noise immunity of the input driverare investigated. Compared w...
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A novel controlled slew-rate (CSR)output driver is presented to reduce the simultane-ous switching noise (SSN). The SSN effects on digitalcircuits and the noise immunity of the input driverare investigated. Compared with traditional CSR out-put driver, a combination of the feedback as well asthe distributed and weighted structure is adopted toimprove the noise performance of the CMOS outputdriver. A prototype circuit is implemented in 0.6-μmCMOS technology with about 3.6 times noise ampli-tude reduction in the ground line, which complies withthe simulation results of HSPICE.
The epitaxial growth of a high-quality silicon layer on double-layer porous silicon by ultra-high vacuum/chemical vapour deposition has been reported. The two-step anodization process results in a double-layer porous ...
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The epitaxial growth of a high-quality silicon layer on double-layer porous silicon by ultra-high vacuum/chemical vapour deposition has been reported. The two-step anodization process results in a double-layer porous silicon structure with a different porosity. This double-layer porous silicon structure and an extended low-temperature annealing in a vacuum system was found to be helpful in subsequent silicon epitaxial growth. X-ray diffraction,cross-sectional transmission electron microscopy and spreading resistance testing were used in this work to study the properties of epitaxial silicon layers grown on the double-layer porous silicon. The results show that the epitaxial silicon layer is of good crystallinity and the same orientation with the silicon substrate and the porous silicon layer.
In this paper a novel digital demodulation method for CPFSK and its realization are introduced which is called phase quantization demodulator (PQD). PQD is a improvement on zero intermediate-frequency zero-crossing de...
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ISBN:
(纸本)0780366778
In this paper a novel digital demodulation method for CPFSK and its realization are introduced which is called phase quantization demodulator (PQD). PQD is a improvement on zero intermediate-frequency zero-crossing demodulator (ZIFZCD). Comparison between PQD, ZIFZCD and conventional cross-correlator is done and the result show that the PQD has less calculation which result in less complexity and power consumption.
In a single-stage multi-bit Σ-Δ modulator, the implementation of the multi-bit quantizer is often area and power consuming. When the bits of the quantizer increase, the scale of the circuit may increase exponentiall...
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ISBN:
(纸本)0780366859
In a single-stage multi-bit Σ-Δ modulator, the implementation of the multi-bit quantizer is often area and power consuming. When the bits of the quantizer increase, the scale of the circuit may increase exponentially and soon become practically impossible. In this paper, a new architecture, the Noise-Reducing Loop, is proposed. It employs a quantizer with only a few bits and achieves much better performance which can only be achieved by using a huge quantizer in the conventional modulators. If accompanied with the Dynamic Quantization algorithm, the modulator can trace the change of the input signal and achieve near optimal performance adaptively in different working conditions.
This paper describes a clock and data recovery circuit that operates at 2.5Gb/s in a 1.8V 0.18um digital CMOS technology. It is a main part of the receive path in a fully integrated CMOS SerDes transceiver. A frequenc...
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This paper describes a clock and data recovery circuit that operates at 2.5Gb/s in a 1.8V 0.18um digital CMOS technology. It is a main part of the receive path in a fully integrated CMOS SerDes transceiver. A frequency-aided PLL-based dual-loop architecture is adopted. To suppress the noise, a ring oscillator composed of differential buffer delay stage is introduced that employs some technique to lower the gain. A special data-triggered phase/frequency detector is also described. A transistor-level simulation shows the overall lock behavior.
A 1GHz analog multiplier with a supply of 1.2V is implemented with a 0.6 micron DPDM standard CMOS technology of CSMC, China. With a shunt-peaked, low noise amplifier (LNA) core, the proposed multiplier features with ...
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A 1GHz analog multiplier with a supply of 1.2V is implemented with a 0.6 micron DPDM standard CMOS technology of CSMC, China. With a shunt-peaked, low noise amplifier (LNA) core, the proposed multiplier features with IIPS of 6.3dBm (for mixer application), conversion grain of 10dB and noise figure of 18dB with a power consumption of 22mW. Several design techniques have been adopted to achieve the target of low noise, low power and high speed. This multiplier can be used as the basic element of a RF mixer.
The equality of the 2ndlaw of thermodynamics had been regarded as the sufficient and necessary condition for a system being in equilibrium for about 150 years. However, such a classical or traditional basic concept sh...
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