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检索条件"机构=State-Key Lab of ASIC & System"
809 条 记 录,以下是61-70 订阅
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High speed radix-16 design of a scalable montgomery multiplier
High speed radix-16 design of a scalable montgomery multipli...
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asicON 2005: 2005 6th International Conference on asic
作者: Fan, Yibo Zeng, Xiaoyang Yu, Yu Wang, Gang Deng, Huang Zhang, Qianling State-Key Lab of ASIC and System Fudan University Shanghai 200433 China
This paper describes an improved version of the Tenca-Todorov-Koç word based radix-8 Montgomery multiplier. It uses radix-16 for fast without adding any hardware, and adjusting the data-path to get shorter critic... 详细信息
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A 3GHz Phase-Locked Loop Design for SerDes Application  16
A 3GHz Phase-Locked Loop Design for SerDes Application
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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022
作者: Yang, Yuting Lyu, Bingrong Ye, Fan Ren, Junyan Fudan University State Key Lab. of Asic & System Shanghai China
A 0.9V high performance 3GHz charge pump phase-locked loop (CP PLL) has been designed in TSMC 28nm CMOS technology, which features high accuracy charge pump (CP) and low phase noise LC voltage-controlled oscillator (L... 详细信息
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A unified 4/8/16/32-point integer IDCT architecture for multiple video coding standards
A unified 4/8/16/32-point integer IDCT architecture for mult...
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2012 13th IEEE International Conference on Multimedia and Expo, ICME 2012
作者: Shen, Sha Shen, Weiwei Fan, Yibo Zeng, Xiaoyang State Key Lab. of ASIC and System Fudan University Shanghai China
4 or 8-point IDCT are widely used in traditional video coding standards. However larger size (16/32-point) IDCT has been proposed in the next generation video standard such as HEVC. To fulfill this requirement, this w... 详细信息
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An efficient packing algorithm based on constraint satisfaction problem technique
An efficient packing algorithm based on constraint satisfact...
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8th Southern Programmable Logic Conference, SPL 2012
作者: Yang, M. Tong, Jiarong State Key Lab. of ASIC and System Fudan University Shanghai China
In this paper, an efficient packing algorithm based on constraint satisfaction problem technique is proposed for contemporary FPGA CLB architecture. No matter how complex the architecture is, there are a limited numbe... 详细信息
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The improvement of the processes of a class of graph-cut-based image segmentation algorithms
The improvement of the processes of a class of graph-cut-bas...
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作者: Niu, Shengxiao Chen, Gengsheng State Key Lab of ASIC and System Fudan University Shanghai201203 China
In this paper, an analysis of the basic process of a class of interactive-graph-cut-based image segmentation algorithms indicates that it is unnecessary to construct n-links for all adjacent pixel nodes of an image be... 详细信息
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A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology  15
A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm ...
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15th IEEE International Conference on asic, asicON 2023
作者: Lyu, Bingrong Ye, Fan Ren, Junyan Fudan University State Key Lab. of ASIC & System Shanghai China
A 6-Gb/s half rate current mode logic (CML) transmitter has been designed in TSMC 28nm CMOS technology, which employs a 3-tap 3-bit feed forward equalizer (FFE), an analog duty cycle correction module (DCC) for half r... 详细信息
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A fully programmable frame synchronization architecture of OFDM systems implemented on a multi-core processor platform
A fully programmable frame synchronization architecture of O...
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2010 10th IEEE International Conference on Solid-state and Integrated Circuit Technology
作者: Fan, Wenhua Huang, Bei Cao, Jialin Chen, Yun Yu, Zhiyi Zeng, Xiaoyang State Key Lab of ASIC and System Fudan University Shanghai 201203 China
This paper presents a fully programmable frame synchronization architecture of OFDM systems implemented on a multi-core processor platform. By utilizing the guard interval in OFDM signals, the coarse symbol synchroniz... 详细信息
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A novel multi-core processor for communication applications
A novel multi-core processor for communication applications
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2010 10th IEEE International Conference on Solid-state and Integrated Circuit Technology
作者: Xiao, Ruijin Quan, Heng You, Kaidi Huang, Bei Zeng, Xiaoyang Yu, Zhiyi State Key Lab of ASIC and System Fudan University Shanghai 201203 China
This paper proposes a novel multi-core processor with SIMD(Single Instruction Multiple Data) ISA (Instruction Set Architecture) and extended register file for communication applications. To acquire better parallel com... 详细信息
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Ferroelectricity of the BiFeO3 prepared by the chemical solution deposition method
Ferroelectricity of the BiFeO3 prepared by the chemical solu...
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Fifth International Conference on Thin Film Physics and Applications
作者: Yang, Caixia Lin, Yinyin Tang, Ting-Ao State Key Lab of ASIC and System Fudan University Shanghai 200433 China
Bismuth ferric thin films were fabricated on Pt/Ti/SiO2/Si substrates by the chemical solution deposition Technique. The films were annealed at different temperature using a rapid thermal processor. DTA-TG and DSC-TG ... 详细信息
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Design of a high parallelism high throughput HSPA+ Turbo decoder  11
Design of a high parallelism high throughput HSPA+ Turbo dec...
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11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (asic), asicON 2015
作者: Cheng, Jieqiong Yang, Qingqing Zhou, Xiaofang State Key Lab of ASIC and System Fudan University Shanghai200433 China
Research in high throughput, high performance Turbo coding systems has an important significance for the development of modern wireless communication systems. This work presents a design of a high parallelism high thr... 详细信息
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