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A 30-mA Compensation-Free Output-Capacitorless analog LDO With Hybrid Adaptive Biasing

IEEE Transactions on Power Electronics 2025年第8期40卷 11182-11196页

作者： Tan, Yee-Chyan Ramiah, Harikrishnan Hatta, Sharifah Fatmadiana Wan Muhamad Lai, Nai Shyan Lim, Chee-Cheow Martins, Rui P. Mak, Pui-In Chen, Yong Universiti Tunku Abdul Rahman Department of Electronic Engineering Faculty of Engineering and Green Technology Kampar31900 Malaysia University of Malaya Department of Electrical Engineering Faculty of Engineering Kuala Lumpur50603 Malaysia Asia Pacific University of Technology and Innovation School of Engineering Kuala Lumpur57000 Malaysia Infinecs Systems Sdn. Bhd. Bayan Lepas Penang11900 Malaysia University of Macau State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST 999078 China Universidade de Lisboa Insitituto Superior Técnico Lisbon1649-004 Portugal Tsinghua University Department of Electronic Engineering Beijing100190 China

This article presents an output-capacitorless low-dropout regulator (OCL-LDO), merging with a hybrid push-pull buffer. The hybrid push-pull buffer implements a dynamic and adaptive biasing push-pull gate driving circuit, achieving stability without needing a complex compensation circuit and external load capacitor. Our devised OCL-LDO can operate with a load current range of 0-30 mA, with a quiescent current of 7 μA at zero load current. The proposed OCL-LDO is fabricated in a 0.18-μm CMOS process with an active area of 0.03 mm2. Measurement results show that with a load current stepping from 0-30 mA and an edge time of 100 ns, the output voltage undershoot is 0.14 V, with a corresponding recovery time of 150 ns. The measured load regulation is 0.207 mV/mA at a supply voltage of 1.15 V and a dropout voltage of 0.15 V. © 1986-2012 IEEE.

关键词： CMOS integrated circuits

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Pulse-Voltage-Based Method of Thermal Parameter Extraction for Thermopile Infrared Sensors

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IEEE SENSORS JOURNAL 2023年第6期23卷 5593-5600页

作者： Yuan, Tianhui Fu, Jianyu Chen, Yong Lu, Yihong Hou, Ying Sun, Guanjun Chen, Dapeng Chinese Acad Sci Inst Microelect Key Lab Microelect Device & Integrated Technol Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuits Beijing 100049 Peoples R China Wuxi IoT Innovat Ctr Co Ltd Wuxi 214135 Jiangsu Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI & IME ECE Macau Peoples R China Chinese Acad Sci Inst Microelect Integrated Circuit Adv Proc Res & Dev Ctr Beijing 100029 Peoples R China

Thermopile infrared (IR) sensors based on the thermoelectric effect are widely applied in industrial and civil fields. Researchers urgently need to develop a technique for in situ online extraction of the sensor's thermal parameters, in order to allow for better analysis of the sensor's performance and to improve its structure. In this work, a pulse-voltage-based self-test method is proposed. The pulse voltage can be generated easily, and only a few data points are required, with simple data processing. The measured results are close to the theoretical values and results from the constant current method proposed in another paper, thus indicating that our method is effective and accurate. In addition, it has strong significance for array testing.

关键词： Sensors Temperature sensors Voltage Thermal conductivity Thermal stability Resistors Thermal resistance Pulse voltage self-test thermal parameters thermopile infrared (IR) sensor

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A 124–152 GHz > 15-dBm $\mathbf{P}_{\text{sat}}$ 28-nm CMOS PA Using Chebyshev Artificial- Transmission-Line-Based Matching for Wideband Power Splitting and Combining

A 124–152 GHz > 15-dBm $\mathbf{P}_{\text{sat}}$ 28-nm CMOS...

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IEEE Symposium on Radio Frequency Integrated Circuits (RFIC)

作者： Jincheng Zhang Tianxiang Wu Yong Chen Junyan Ren Shunli Ma State Key Laboratory of ASIC &#x0026 System Fudan University China State-Key Laboratory of Analog &#x0026 Mixed-Signal VLSI IME/ECE-FST University of Macau China

ISBN: (数字)9781665496117

ISBN: (纸本)9781665496124

This paper presents a 124–152 GHz power amplifier (PA) with >15 dBm saturation output power $(\mathbf{P}_{\text{sat}})$ in a 28-nm CMOS process. Low-coupling transformer-based fourth-order matching networks are used to extend the bandwidth (BW) with low insertion loss and compact area. A four-way Chebyshev-type artificial-transmission-line-based power combiner is proposed to further improve the output power without sacrificing BW. The measurement results show that this P A can achieve a peak gain of 22.6 $\mathbf{dB}$ with 28 GHz 3-dB BW. The in-band $\mathbf{P}_{\mathbf{sat}}$ is >15 dBm with a maximum output power of 16.2 dBm at 135 GHz. The total area of the chip is $\mathbf{0.66}\mathbf{\times}\mathbf{0.73}\ \mathbf{mm}^{\mathbf{2}}$ •

关键词： Semiconductor device measurement Power combiners Power amplifiers Radar Chebyshev approximation Radiofrequency integrated circuits Circuit faults

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A 0.15-V, 44.73% PCE charge pump with CMOS differential ring-VCO for energy harvesting systems

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analog INTEGRATED CIRCUITS AND signal PROCESSING 2022年第1期111卷 35-43页

作者： Churchill, Kishore Kumar Pakkirisami Ramiah, Harikrishnan Chong, Gabriel Ahmad, Mohd Yazed Yin, Jun Mak, Pui-In Martins, Rui P. Univ Malaya Fac Engn Dept Elect Engn Kuala Lumpur 50603 Malaysia Univ Malaya Fac Engn Dept Biomed Engn Kuala Lumpur 50603 Malaysia Univ Macau State Key Lab Analog & Mixed Signal VLSI IME Macau Peoples R China Univ Macau Fac Sci & Technol ECE Macau Peoples R China Univ Lisbon Inst Super Tecn Lisbson Portugal

This paper proposes a dynamic voltage frequency scaling technique (DVFS) for a CMOS differential bootstrapped ring-voltage controlled oscillator (DBRO), implemented in a 3-stage cross-coupled charge pump (CC-CP), for energy harvesting (EH) applications. A circuit applying this technique known as split input-supply, fabricated in the 130-nm CMOS, compares a signal with an input range of 0.15-0.5 V along with a load of 100 k-1 M omega with an incremental step of 100 k and 2 M omega, respectively. The technique allows the DVFS-DBRO to operate with optimum frequency and lower power consumption, which improves the power conversion efficiency (PCE) as well as establishes a wide energy harvesting range. The circuit observes a 44.73% of PCE with 0.15 V input voltage when driving a 2 M omega load. DVFS also offers a twofold clock boosting of the input voltage without the voltage scaling effect, which improves the charge-pump conduction at low input voltage and allows a gate-to-source input voltage of 0.5 V. These characteristics improve the robustness of the proposed technique and exhibits great potential for a wide input range of EH applications.

关键词： Charge pump DC-to-DC conversion Dynamic voltage frequency scaling (DVFS) Energy harvesting Ring-voltage controlled oscillator (RO)

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Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2022年第6期69卷 2564-2569页

作者： Guo, Mingqiang Sin, Sai-Weng Qi, Liang Xu, Dengke Wang, Guoxing Martins, Rui P. Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau FST ECE Macau Peoples R China Shanghai Jiao Tong Univ Dept Micro Nano Elect Shanghai 200240 Peoples R China Amicro Semicond Co Ltd Zhuhai 519000 Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This brief presents an overview of recent background timing mismatch calibration techniques in time-interleaved ADCs. Regarding the methods of detecting timing skew, the brief divides the existing methods into two categories: a) strategies based on deterministic equalization and b) techniques based on the statistical information of the input signal. Similarly, we can also divide timing skew correction into analog tuning and digital processing. The brief reviews previous works comparatively with these different methods and summarizes their pros and cons.

关键词： Timing Calibration Bandwidth Very large scale integration Finite impulse response filters Clocks Tuning Time-interleaved ADC timing mismatch background calibration

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A 0.01-mm² 1.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase

A 0.01-mm<SUP>2</SUP> 1.2-pJ/bit 6.4-to-8Gb/s Reference-less...

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IEEE MTT-S International Microwave Symposium (IMS)

作者： Zhao, Xiaoteng Chen, Yong Zheng, Xuqiang Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI Taipa Macao Peoples R China Univ Macau IME FST ECE Taipa Macao Peoples R China Chinese Acad Sci Inst Microelect Beijing Peoples R China

ISBN: (纸本)9781665403078

This paper reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) without both external reference and separate frequency detector. Specifically, our bang-bang phase detector incorporates the intrinsic three phases with a 2 pi/3 interval of the three-stage ring oscillator to deliberate the clock-selected strobe-point scheme, resulting in substantial hardware relaxation for automatic frequency acquisition. Together with the aid of a hybrid control circuit, the BBCDR can capture 6.4-to-8Gb/s data-rate variation automatically. Designed in a 65nm CMOS technology, our BBCDR achieves an energy efficiency of 1.2pJ/bit and 0.58UI(PP) jitter tolerance at 200MHz jitter frequency, while occupying a tiny area of similar to 0.01 mm(2)

关键词： CMOS ring oscillator (RO) bang-bang clock and data recovery (BBCDR) frequency detector (FD) strobe point (SP) reference (REF) frequency acquisition clock selection

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A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE

A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Qua...

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IEEE Asia-Pacific Conference on Circuits and Systems

作者： Zhiyang Zhang Xi Wang Yong Chen Junyan Ren Shunli Ma State Key Laboratory of ASIC & System Fudan University Shanghai China State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST University of Macau Macau China

In this paper, a 60-GHz CMOS balanced power amplifier (PA) is proposed. Two miniaturized quadrature hybrids are utilized to realize power splitting and power combining. The compact hybrids can achieve good input and output matching performances. Transistor-layout optimization is taken into consideration to boost the output power and improve the power-added efficiency (PAE). The balanced PA is designed in 65-nm bulk CMOS and all the electromagnetic (EM) simulations of passive devices are executed in the EM tool. Post-layout simulation results show that the proposed balanced PA realizes a small-signal gain of 29.1 dB at 60 GHz with an 11-GHz bandwidth. With a 1.2-V supply voltage and 300-mW power consumption, the balanced PA achieves a saturated output power of 19.0 dBm and 24.4% peak PAE at 60 GHz, which is suitable for 60-GHz wireless systems.

关键词： Wireless communication Simulation Power amplifiers Bandwidth Voltage Hybrid power systems Transistors

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Reconfigurable Filtering Power Divider With Arbitrary Operating Channels Based on External Quality Factor Control

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第11期69卷 4395-4403页

作者： Xu, Jin-Xu Huang, Mo Zhan, Wan-Li Zhang, Xiu Yin Univ Macau State Key Lab Analog & Mixed Signal VLSI Dept Elect & Comp Engn ECE Inst MicroelectFac Sci & Technol FST Macau Peoples R China South China Univ Technol Sch Microelect Guangzhou 510641 Peoples R China South China Univ Technol Engn Res Ctr Short Distance Wireless Commun & Net Minist Educ Sch Elect & Informat Engn Guangzhou 510641 Peoples R China

In this paper, we propose a scheme to design the reconfigurable filtering power divider with arbitrary operating channels based on external quality factor (Q(e)) control. By using an input feeding line, n resonators, and m output feeding lines, the nth -order m-way filtering power divider topology can be obtained with a simple configuration. A coupled-line output feeding structure loading with multiple PIN diodes is proposed to adjust the output Q(e) values. Design theories for obtaining the desired Q(e) values are provided. Then, the filtering power divider can be fully reconfigured in the states with one to in operating channels. Good input matching can be achieved without using an additional reconfigurable impedance matching network in all these states, resulting in a size and loss reduction. For verification, a 2nd-order 4-way reconfigurable filtering power divider is designed, fabricated, and measured. As compared to the reported reconfigurable power dividers, the proposed design shows the merits of fully reconfigurable operating channels, favorable filtering responses, low insertion losses, high isolation, and a simple structure.

关键词： Arbitrary operating channels external quality factor control high isolation low loss reconfigurable filtering power divider simple structure

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A Power-Harvesting CGM Chiplet Featuring Silicon-Based Enzymatic Glucose Sensor 44

A Power-Harvesting CGM Chiplet Featuring Silicon-Based Enzym...

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44th Annual International Conference of the IEEE-Engineering-in-Medicine-and-Biology-Society (EMBC)

作者： Wang, Ting-Hsun Li, Zhuhao Liang, Bo Cai, Yu Wang, Zhiyu Yang, Changgui Luo, Yuxuan Sun, Jiabao Ye, Xuesong Chen, Yong Zhao, Bo Zhejiang Univ Inst VLSI Design Hangzhou 310027 Peoples R China Zhejiang Univ Dept Biomed Engn & Instrument Sci Hangzhou 310027 Peoples R China Zhejiang Univ Micronano Fabricat Ctr Hangzhou 310027 Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI Taipa Macao Peoples R China Univ Macau IME ECE FST Taipa Macao Peoples R China

ISBN: (数字)9781728127828

ISBN: (纸本)9781728127828

Diabetes has become a leading cause of death and disability in the past decades. Continuous glucose monitoring (CGM) is a prevailing technique to determine the glucose level and provide in-time treatment. However, conventional CGM systems combine an electrochemical sensor with a CMOS chip, suffering from bulky size and interface issues. Integrating the CGM sensor on silicon is potential to miniaturize the CGM system and reduce the cost, while the recent silicon-based sensors show limited detection range and sensitivity. In this work, we present a silicon-based CGM chiplet with wireless power transfer (WPT) and real-time wireless telemetry. Fabricated on a single silicon substrate, the chiplet consists of a silicon-based CGM sensor, a power-harvesting wireless-telemetry chip, and a silicon-based antenna. Measured results show that the chiplet achieves a sensitivity of 4 mu ***(-2) and a linear detection range of 0-10 mM. Based on WPT and backscattering communication, the chiplet consumes 18.8 m W power in glucose telemetry.

关键词： Glucose sensors Antenna measurements Semiconductor device measurement Sensitivity Silicon Glucose Telemetry

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Design and Implementation of a Low Power Switched-Capacitor-Based analog Feature Extractor for Voice keyword Spotting

Design and Implementation of a Low Power Switched-Capacitor-...

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IEEE Asia-Pacific Conference on Circuits and Systems

作者： Feifei Chen Ka-Fai Un Wei-Han Yu Pui-In Mak Rui P. Martins The State-Key Laboratory of Analog and Mixed-Signal VLSI/IME and FST-ECE University of Macau Macao China on-leave from the Instituto Superior Técnico UL Portugal

A low-power keyword spotting (KWS) is demanding for the smart human-device interface. The conventional analog feature extractor utilizes an analog filter bank that consumes large power and area. This paper presents a KWS with a low-power switched-capacitor-based feature extractor. The feature extractor employs two pipelining time-domain convolutional neural networks (TD-CNNs) to extract sufficient features for KWS. The TD-CNNs utilize sparsity aware computation (SAC) and sparsified quantization (SQ) for a 4-bit weight quantization. The features are quantized to 2-bit for further classification by an off-chip deep neural network. The analog feature extractor is designed in a 55-nm CMOS process and post-layout simulation is provided. It consumes 4.4 µW at a 1.2-V power supply, with an area of 0.39 mm 2 . It achieves an accuracy of 92.2% for the google command dataset (GSCD) with five classes.

关键词： Semiconductor device modeling Quantization (signal) Power supplies Neural networks Switches Feature extraction System-on-chip

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