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A 4T/Cell Amplifier-Chain-Based XOR PUF With Strong Machine Learning Attack Resilience

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第1期69卷 366-377页

作者： Zhang, Jieyun Xu, Chongyao Law, Man-Kay Jiang, Yang Zhao, Xiaojin Mak, Pui-In Martins, Rui P. Univ Macau Inst Microelect FST State Key Lab Analog & Mixed Signal VLSIECE Dept Macau 999078 Peoples R China Shenzhen Univ Coll Elect & Informat Engn Shenzhen 518060 Peoples R China Univ Macau FST ECE Dept State Key Lab Analog & Mixed Signal VLSI Macau 999078 Peoples R China

This paper presents an amplifier-chain-based XOR physical unclonable function (AC-XOR PUF), with the process- and/or bias-dependent voltage and amplification information of two identical amplifier chains serving as the entropy sources. The current-biased PUF cell using only 4 NMOS transistors achieves a small area with reduced temperature and supply sensitivity. Optimization on both the stage gain and stage number can reduce the input-referred noise (IRN) and improve the PUF reliability. We further employ an XOR gate to process the amplifier-chain outputs for the final response to improve the energy efficiency and uniqueness. The process- and bias-dependent stage amplification and the nonlinear amplifier-chain multiplication, which can significantly increase the number of modeling parameters and introduce a complex decision boundary respectively, can effectively resist machine learning (ML) modeling attacks. Fabricated in standard 65nm CMOS, the proposed AC-XOR PUF occupies an active area of 6845 mu m(2). Without discarding any challenge-response pairs (CRPs), this work features a measured worst case bit error rate (BER) of 5.70% across 1.06 similar to 1.55V and -30 similar to 125 degrees C, while demonstrating a reliability (intra-die HD) and uniqueness (inter-die HD) of 0.58% and 49.92%, respectively. It also achieves a ML prediction accuracy of 50.72% using 80x 80x80 artificial neural network (ANN) with 1M CPRs as training set.

关键词： Amplifier chain hardware security machine learning attack physical unclonable function (PUF)

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A Radio-Frequency Cross-Connected Rectifier With LC Source Degeneration

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第2期71卷 573-582页

作者： Chen, Qiujin Huang, Mo Xia, Tian Yin, Jun Liu, Haiwen Martins, Rui P. Lu, Yan Univ Macau Inst Microelect Dept Elect & Comp Engn ECE State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Fac Sci & Technol FST Macau Peoples R China Xi An Jiao Tong Univ Sch Elect & Informat Engn Xian 710049 Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI State Key Lab AMSV Macau Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This paper proposes a radio-frequency (RF) cross-connected (CC) rectifier with LC source degeneration (CCLC). The LC network resonates at twice of the working RF frequency, shaping the drain-source and gate-source voltages of the rectifying transistors of the CC rectifier. As a result, the proposed scheme reduces the transistors' reverse current and the shoot-through current, and thus the root mean square current of the switches, improving the power conversion efficiency (PCE). Meanwhile, it has a better input impedance matching over a wide input power range from the voltage reshaping. Subsequently, we implement the CCLC topology in both one-stage and two-stage CC rectifiers. To reduce the silicon area, we design coupled inductors for the two LC networks of the two-stage CCLC rectifier. We fabricated the rectifiers using a 65-nm CMOS process. The measured PCE of the one-stage and two-stage rectifiers are 67.6% and 61.2%, respectively. The proposed scheme has a wider dynamic range than previous works.

关键词： Rectifier radio frequency cross-connected source de generation energy harvesting

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A 12-to-1 V Quad-Output Switched-Capacitor Buck Converter With Shared DC Capacitors

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IEEE JOURNAL OF SOLID-state CIRCUITS 2023年第12期58卷 3492-3502页

作者： Hu, Tingxu Huang, Mo Martins, Rui P. Lu, Yan Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Fac Sci & Technol FST Dept Elect & Comp Engn ECE Macau Peoples R China

This article presents a 12-to-1 V quad-output switched-capacitor buck (SCB) converter with shared dc capacitors ( C(DC)s). First, we proposed single-output SCB achieving a high efficiency, with small switch area and small inductor volume under several-ampere conditions. Each single-output SCB has two C(DC)s. Second, based on the single-output SCB, we proposed multiple-output SCB converter that shares the two C(DC)s among the channels. The C-DC-sharing improves the power density and efficiency under unequal-load conditions. Third, we eliminate cross-regulation in a conventional energy-store-device-sharing topology through current mode (CM) control. Besides, we use a capacitor-sourced gate drive scheme that is highly compatible with the SCB, removing the bootstrap and gate drive supply voltage generation circuits. Fabricated in a 180-nm BCD process, this design achieves a measured peak efficiency of 90.4%, and 48 mA/mm(3) power density with 85% efficiency. To our best knowledge, this is one of the first 12-to-1 V integrated hybrid converter with multiple outputs reported.

关键词： 12-to-1 V hybrid dc-dc converter multiple-output power conversion efficiency switched-capacitor buck (SCB) converter

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A 3.5~7.5 GHz GaAs HEMT Cryogenic Low-NoiseAmplifier Achieving 5 Kelvin Noise Temperature for Qubits Measurement

A 3.5~7.5 GHz GaAs HEMT Cryogenic Low-NoiseAmplifier Achievi...

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2023 IEEE/MTT-S International Microwave Symposium, IMS 2023

作者： Peng, Yatao Zhong, Youpeng Guo, Zechen Liu, Song Yu, Dapeng University of Macau State Key Lab. of Analog and Mixed-Signal VLSI IME/ECE of FST China Shenzhen International Quantum Academy China SUSTech Shenzhen Institute for Quantum Science and Engineering China

ISBN: (纸本)9798350347647

The measurement of the fast-increasing number of qubits necessitates the use of a large number of specialized cryogenic low-noise amplifiers (LNAs).). This work presents a broadband LNA designed with discrete GaAs HEMT components which operate well at ~3.6 K temperature. The dual-frequency optimum noise matching network and output matching elements of the first stage were employed to optimize the equivalent noise temperature (NT) and the input return loss in a wideband. Measurement results at 3.6 K ambient temperature show that the LNA achieved an equivalent NT of 30 dB in the 3.5 GHz to 7.5 GHz band with a minimum of 5 Kelvin at ~6.5 GHz. The best visibility of ~0.891 is achieved when using the LNA to observe a superconducting transmon qubit without using a JPA. © 2023 IEEE.

关键词： Low noise amplifiers

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A 124-to-152-GHz Power Amplifier Exploiting Chebyshev-Type Two-Section Wideband and Low-Loss Power-Combining Technique in 28-nm CMOS

A 124-to-152-GHz Power Amplifier Exploiting Chebyshev-Type T...

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作者： Zhang, Jincheng Wang, Yujia Chen, Yong Ren, Junyan Ma, Shunli Fudan University State Key Laboratory of Asic and System Shanghai200433 China University of Macau State-Key Laboratory of Analog and Mixed-Signal Vlsi and IME/ECE-FST China

This article presents a high-power wideband power amplifier (PA) with a four-way power-combining technique for $D$ -band high-resolution radar. The power combiner is based on a two-section Chebyshev impedance converter to achieve a large bandwidth (BW) and is realized with slow wave coplanar waveguides (S-CPWs) to reduce the insertion loss and chip area. Therefore, our developed technique can provide broadband and low-loss power-combining scheme in a very compact size. A high-power PA with four-way combining has been fabricated in a 28-nm CMOS bulk technology. The unit PA uses low- $k$ transformer-based coupled-resonator networks to realize wideband matching. The measured results of the PA prototype demonstrate the peak gain of 22.6 dB, the saturated output power of 16.2 dBm, and the peak power added efficiency of 8.6% at 135 GHz with a 3-dB BW of 28 GHz from 124 to 152 GHz. Meanwhile, the total area of this PA die is merely 0.66 $\times $ 0.73 mm. © 1963-2012 IEEE.

关键词： Power amplifiers

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Floating-Domain Integrated GaN Driver Techniques for DC-DC Converters: A Review

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第9期70卷 3790-3805页

作者： Mu, Xuchu Zhao, Guangshu Zhao, Anyang Jiang, Yang Law, Man-Kay Takamiya, Makoto Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI IME Macau Peoples R China Univ Macau Dept ECE FST Macau Peoples R China Univ Tokyo Inst Ind Sci Tokyo 1538505 Japan Univ Lisbon Inst Super Tecn P-1649004 Lisbon Portugal

This paper presents the design challenges and advanced circuit techniques of integrated gate drivers for non-isolated buck converters using gallium nitride (GaN) devices to achieve fast switching and high conversion efficiency. Focusing on the essential tradeoff considerations, we first explain the detailed circuit-level issues of realizing normal and safe operations regarding integration feasibility, device safety, operation reliability, and power-stage loss alleviation when driving a GaN switch. Accordingly, we review the state-of-the-art techniques for improving various aspects of the performance, including on-chip bootstrapping enhancement, over-voltage and false-switching prevention, electromagnetic interference (EMI) noise suppression, and adaptive driving optimization. We further highlight the feature advantage of distinct techniques in specific performance/function aspects, aiming to bring GaN driver design insights and providing technical references regarding the technical superiority and limitations of improving the overall converter performance.

关键词： Adaptive dead time bootstrapping buck converter EMI GaN gate driver integration reliability

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A Cryo-CMOS Wideband Mode-Switching Class-F VCO With Harmonic-Resonance Self-Alignment

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IEEE JOURNAL OF SOLID-state CIRCUITS 2025年

作者： Wu, Yue Peng, Yatao Ruffino, Andrea Benserhir, Jad Yin, Jun Martins, Rui P. Mak, Pui-In Charbon, Edoardo Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau FST ECE Macau Peoples R China Ecole Polytech Fed Lausanne EPFL Adv Quantum Architecture Lab CH-2002 Neuchatel Switzerland Swiss Fed Inst Technol Integrated Devices Elect & Syst Lab CH-8092 Zurich Switzerland Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Inst Microelect Macau Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This article presents a cryogenic mode-switching class-F voltage-controlled oscillator (VCO) aimed at addressing the demand for wideband, low phase noise (PN) local oscillator signals in cryo-CMOS quantum controllers. First, to resolve the issues of manual alignment of harmonics and resonances, and excessive drain-to-gate gain leading to reliability concerns in transformer (XFMR)-based class-F VCOs, a single-core class-F VCO architecture with harmonic-resonance self-alignment property was constructed by utilizing a symmetrical and XFMR-less dual-mode resonator (DMR), which features a pair of concurrently tunable and fixed-ratio (3:1) resonant frequencies. Since the pseudo-square oscillating voltage waveforms are directly fed back to the gates, a sharper class-F oscillation is achieved to reduce the impulse sensitivity function (ISF) even without the drain-to-gate gain. Then, the lossless mode-switching technique is introduced into two coupled single-core class-F VCOs to extend the frequency tuning range (FTR) and gain about 3-dB PN reduction. The coupling realized by inductive and small magnetic elements does not disrupt the self-alignment characteristics for under mode-switching operation. Large-dimension transistors were employed to design the negative transconductance cells to suppress flicker noise and channel shot noise at cryogenic temperatures (CTs). Furthermore, the worsened nonlinearity in MOSFETs at CTs is exploited to enhance the waveform shape of class-F oscillations. The designed and fabricated VCO prototype achieves 5.3-to 10.6-GHz FTR with a best PN of -153.1 dBc/Hz at 10-MHz offset at 3.7 K, corresponding to a best figure of merit (FoM) and FoM for FTR (FoM(T)) of 203.8 and 220.3 dBc/Hz, respectively.

关键词： Voltage-controlled oscillators Resonant frequency Harmonic analysis Tuning Oscillators Impedance Cryogenics Inductors Transformers Inductance Class-F oscillator cryo-CMOS frequency tuning range (FTR) harmonic-resonance self-alignment mode-switching (MS-VCO) quad-mode resonator (QMR) quantum computing

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A 10.5 W, 93% Efficient Dual-Path Hybrid(DPH)-Based DC-DC Converter Incorporating a Continuous-Current-Input Switched-Capacitor Stage and Enhanced IL Reduction for 12 V/24 V Inputs

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第12期70卷 5482-5495页

作者： Ma, Qiaobo Zhang, Xiongjie Zhao, Anyang Li, Huihua Jiang, Yang Law, Man-Kay Takamiya, Makoto Martins, Rui P. Mak, Pui-In Univ Macau State Key Lab Analog & Mixed Signal VLSI IME Macau Peoples R China Univ Macau Dept ECE FST Macau Peoples R China Univ Tokyo Inst Ind Sci Tokyo 1538505 Japan Univ Lisbon Inst Super Tecn P-1649004 Lisbon Portugal

This work proposes a high-step-down switched-capacitor (SC) hybrid DC-DC converter that effectively addresses the conduction loss in the inductor and power switches. Specifically, an architecture combining a dual-path hybrid (DPH)converter at the input, and a continuous-current-input SC (CISC)stage at the output, achieves superior performance in reducing the inductor DC current (I-L,I-DC)compared to the existing single-inductor two-flying-capacitor (1L-2C(F))converters. Also, the converter exploits low-voltage (LV) switches to handle a substantial portion of the current, diminishing the reliance on the inductor or high-voltage (HV) switches. Consequently, this approach enhances the efficiency and on-chip power/current density. The converter, implemented in 180-nm BCD, integrates monolithic power switches, drivers, and control circuitry. It is capable of regulating an output voltage within the range of 1.2 to3.5 V, accommodating a 12 V/24 V-input. The peak efficiency is93% and the on-chip current density is 0.638A/mm(2). The load current delivery is up to 3 A, even using a compact inductor with a DC resistance (DCR) of 200 m Omega.

关键词： DCR loss current density dual-path hybrid topology inductor current reduction switched-capacitor

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A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2023年第5期51卷 1988-2015页

作者： Wang, Lin Chen, Yong Yang, Chaowei Zhou, Xionghui Han, Mei Stefano, Crovetti Paolo Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI & IME ECE Macau Peoples R China Politecn Torino Dept Elect & Telecommun DET Turin Italy Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This paper reports a bang-bang clock and data recovery circuit (BBCDR) with an ultra-wide capture range. The circuit exhibits automatic frequency capture and phase locking over a wide 6-to-38 Gb/s range without using a frequency detector, allowed by a recently proposed deliberate-current-mismatch technique. Moreover, we accurately obtain an eight-phase clock through analog interpolation of quadrature signals over the whole wide frequency range by introducing a tunable capacitor array before an inverter-based phase interpolator. A 65-nm prototype of the developed BBCDR occupies an area of 0.07 mm(2) and attains a bit error rate of less than 10(-12) under a continuously variable input frequency, with a total power consumption of 24.6 mW for a 32-Gb/s non-return-zero input, thus leading to 0.769-pJ/bit energy efficiency.

关键词： bang-bang clock and data recovery (BBCDR) current mismatch frequency detector (FD) hybrid control circuit (HCC) phase interpolator (PI) ring oscillator (RO) R-2R digital-to-analog converter (DAC) switched-capacitor (SC) array wide capture range

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A Capacitor-Cross-Connected Boost Converter With Duty Cycle <0.5 Control for Extended Conversion-Ratio and Soft Start-Up

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第10期69卷 4272-4283页

作者： Hu, Tingxu Huang, Mo Lu, Yan Martins, Rui P. Univ Macau Fac Sci & Technol FST Dept Elect & Comp Engn ECEInst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China

The series-capacitor boost converter (SCBC) requires a duty cycle (D) >= 0.5 control, otherwise has issues of power switch overstress and inductor currents imbalance. Then, we cannot use the SCBC in wide conversion ratio (CR) applications that require CR < 4. Meanwhile, the D >= 0.5 control does not allow D to increase smoothly from 0 during startup, causing severe inrush inductor currents. As a solution, we propose two control schemes on the capacitor-cross-connected (CCC) boost converter, which is the symmetric version of the SCBC. With the proposed hard-charging control, the CCC converter allows D < 0.5 without overstress or imbalance issues, thus extending the CR range and facilitating a soft start-up. In addition, we propose a soft-charging control that enhances the efficiency for 3 < CR < 4. We study the output impedance and CR expressions under these two types of controls. Finally, we propose a compact centrosymmetric floorplan that reduces the switching nodes' ringing, verifying the proposed schemes with a 2.8-to-8.4-V input / 24-V output prototype converter. It exhibits a soft start-up with the proposed control. Under an 8-V input voltage and 1.5-A output current, the peak efficiency of the proposed hard-charging and soft-charging control is 94.7% and 96.3%, respectively.

关键词： Boost converter hybrid dc-dc converter extended conversion ratio soft start-up

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