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IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

作者： Li, Huihua Ma, Qiaobo Mu, Xuchu Rang, Yang Law, Man-Kay Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI IME FST Macau Peoples R China Univ Lisbon lnst Super Tecnico Lisbon Portugal

ISBN: (纸本)9781665450737

This paper presents two adaptive line-transient enhancement techniques for a dual-path hybrid converter (DPHC) to eliminate the input (VIN) variation-induced output (VOUT) ripples. Tackling the intrinsic hard-charging limitation in the DPHC, we propose a topology operation reconfiguration and a power switch modulation technique to reduce the direct-coupled hard-charging current from VIN to VOUT. The proposed controller features adaptive state detection and switching functions, which ensure a low output ripple over a wide load-current range. Besides, the controller is assisted by a V-2-mode pulse-width modulation control with reconfigurable adaptive-amplitude ramp generation to achieve a fast load-transient response. A DPHC with the proposed control techniques implemented in a 180nm CMOS process can regulate a 1V output from a 4-to-6V input. It realizes a VOUT overshoot and undershoot as low as 1% of the DC level under a 1-V V-IN step change. The corresponding VOUT transient ripple reduction can be over 96% and 88% in the light and full load conditions, respectively, when compared with the existing DPHC operation mode. The conversion efficiency is up to 92.5% under 1-A load current (I-load) and 85.8% under a maximum Iload target of 5A.

关键词： DC-DC converter dual-path hybrid line transient switched-capacitor

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SUPERWETTABILITY BASED MICROARRAYS FOR HIGH-THROUGHPUT SINGLE-MICROSPHERE ISOLATION ON DIGITAL MICROFLUIDICS 26

SUPERWETTABILITY BASED MICROARRAYS FOR HIGH-THROUGHPUT SINGL...

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26th International Conference on Miniaturized Systems for Chemistry and Life Sciences, MicroTAS 2022

作者： Meng, Li Li, Mingzhong Law, Man-Kay Mak, Pui-In Martins, Rui P. State-key Laboratory of Analog and Mixed-Signal VLSI IME and FST-ECE University of Macau China Instituto Superior Técnico Universidade de Lisboa Portugal

ISBN: (纸本)9781733419048

This work proposes a digital microfluidics (DMF) functional substrate with super-wettability contrast for high-throughput single microsphere isolation within an array of 810 individual microdroplets. By passively dispensing a mother droplet with a concentration of 2 mg/mL, this work achieves a state-of-the-art single microsphere isolation rate within individual microdroplets of up to 36.75% on DMF platform. The proposed technique can facilitate medical, biological, and optical applications requiring high throughput and precision single microsphere analysis. © 2022 MicroTAS 2022 - 26th International Conference on Miniaturized Systems for Chemistry and Life Sciences. All rights reserved.

关键词： Digital microfluidics

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A Level Shifter With Almost Full Immunity to Positive dv/dt for Buck Converters

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第11期70卷 4595-4604页

作者： Yang, Yunzhe Huang, Mo Du, Sijun Martins, Rui P. Lu, Yan Univ Macau Dept Elect & Comp Engn ECE State Key Lab Analog & Mixed Signal VLSI Fac Sci & Technol FST Macau Peoples R China Univ Macau Inst Microelect Macau Peoples R China Delft Univ Technol Dept Microelect NL-2628 CD Delft Netherlands

High-frequency buck converters need a fast transi-tion of switching nodes (high dv/dt). Such high dv/dt, especially the positive one, can cause malfunction of a conventional pulse-triggered active-coupled (PTAC) level shifter that is used to control the high-side NMOS switch. In this work, we first discuss the dv/dt immunity of conventional PTAC level shifters. Subsequently, we propose a new scheme to block the noise current during the dv/dt sequence, allowing an almost full immunity to the positive dv/dt. With this scheme, the maximum dv/dt is determined by how well the circuitry is protected from the overvoltage during the dv/dt sequence. We design a 20-V buck converter with this level shifter, fabricated in 180-nm BCD process. Experimental results show it works correctly under a 67-V/ns dv/dt.

关键词： DC-DC converter level shifter buck converter dv/dt immunity

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A Switchless Dual-core Triple-Mode VCO Achieving 7.1-to-15.7 GHz Frequency Tuning Range and 202.1 dBc/Hz Peak FoM at 3.7 Kelvin

A Switchless Dual-core Triple-Mode VCO Achieving 7.1-to-15.7...

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IEEE Symposium on Radio Frequency Integrated Circuits (RFIC)

作者： Yue Wu Yatao Peng Benhao Huo Jun Yin Rui P. Martins Pui In Mak State Key Lab. of Analog and Mixed-Signal VLSI IME/ECE of FST University of Macau China Instituto Superior Técnico Universidade de Lisboa Portugal

ISBN: (数字)9798350359473

ISBN: (纸本)9798350359480

We reported a dual-core triple-mode voltage-controlled oscillator (VCO) to adapt to the low power consumption and large frequency tuning range (FTR) of the signal source in quantum interface systems. We proposed using only magnetic and inductive tuning elements for resonance splitting to construct the VCO’s triple-mode LC tank. This avoids the FTR sacrifice when using a conventional capacitive tuning element to build the multi-mode tank. To reduce the power consumption of the negative trans-conductance (-G M ) cells in the multicore multi-mode VCO, we proposed a structure that provides a triple oscillating mode with only two -G M cores. In addition, to overcome the deterioration of phase noise (PN) due to the switch-on resistances, we introduced a switching -GM technique for mode selection without using the MOSFET switches. The wideband VCO was specifically designed for cryogenic operation, utilizing a 28 nm CMOS technology. The measured results demonstrate an FTR of 7.1-15.7 GHz (75.4%) and a peak figure-of-merit (FoM) of 202.1 dBc/Hz at 3.7 Kelvin.

关键词： Phase noise Power demand Multicore processing Voltage-controlled oscillators Kelvin Switches Cryogenics

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Modeling-Attack-Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability

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IEEE INTERNET OF THINGS JOURNAL 2023年第18期10卷 16300-16315页

作者： Xu, Chongyao Zhang, Litao Law, Man-Kay Zhao, Xiaojin Mak, Pui-In Martins, Rui P. Univ Macao State Key Lab Analog & Mixed Signal VLSI Inst Microelect Macau Peoples R China Univ Macao FST ECE Macau Peoples R China Shenzhen Univ Coll Elect & Informat Engn Shenzhen 518060 Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This article presents an obfuscated-interconnection physical unclonable function (OIPUF) to resist modeling attacks. By introducing nonlinear operations through exploiting the random interconnections of delay stages, the proposed OIPUF can theoretically improve the physical unclonable function (PUF) security while consuming the same hardware resources as the conventional XOR arbiter PUF ( XOR APUF). We further propose the metastability-detection (MD) arbiter to effectively improve the PUF reliability. Implemented on Xilinx Artix-7 field-programmable gate array, both the proposed (64,4)- and (64,8)-OIPUF demonstrate a good reliability and uniformity, with the proposed (64,8)-OIPUF showing a better uniqueness and strict avalanche criterion (SAC) performance. Measurement results also show that the proposed MD arbiter can reduce the bit error rate (BER) of the (64,4)- and (64,8)-OIPUF by >= 68x and >= 48x at up to 100 degrees C, respectively. Evaluated using the logistic regression (LR), artificial neural network (ANN), and covariance matrix adaptation-evolution strategy (CMA-ES) machine learning (ML) algorithms, the proposed (64,4)- and (64,8)-OIPUF can achieve a worst case prediction accuracy of 61.47% and 50.59% with up to 10M challenge-response pairs as training set, respectively, demonstrating a significant improvement over similar prior arts.

关键词： Field-programmable gate array (FPGA) machine learning (ML) modeling attack obfuscated interconnection (OI) physical unclonable function (PUF)

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Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2025年第3期72卷 439-443页

作者： Xu, Tailong Li, Haoran Meng, Xi Zhan, Xiangxun Peng, Yatao Yin, Jun Yang, Shiheng Fan, Chao Huang, Zhixiang Martins, Rui P. Mak, Pui-In Hefei Univ Sch Adv Mfg Engn Dept Elect & Informat Engn Hefei 230601 Anhui Peoples R China Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Fac Sci & Technol Dept Elect & Comp Engn Macau Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME ECE FST Macau Peoples R China Univ Elect Sci & Technol China Sch Integrated Circuit Sci & Engn Chengdu 610054 Sichuan Peoples R China Xi An Jiao Tong Univ Sch Microelect Xian 710049 Shannxi Peoples R China Anhui Univ Anhui Higher Educ Inst Key Lab Electromagnet Environm Sensing Hefei 230601 Anhui Peoples R China

This brief analyzes the phase noise (PN) and reference (REF) spur performance of the reference-sampling (RS) PLL when the total sampling capacitor (C-S) is reduced to save the power consumption of the crystal oscillator (XO) buffer. Based on the analysis, the saved power consumption from the XO buffer can be utilized to improve the PN of the voltage-controlled oscillator (VCO), which compensates for the in-band PN degradation induced by the C-S reduction. Based on this theme, we can reduce the total power consumption of the RS-PLL and the XO buffer without degrading the output root-mean-square (RMS) jitter by reducing C-S if a VCO with a high figure-of-merit (FoM) and a low 1/f(3) PN corner frequency is availab.e. A type-II RS-PLL prototype utilizing a gain-boosting RS phase detector to suppress the voltage-to-current (GM) circuit noise is designed to verify the presented design strategy. With the aid of an inverse-class-F VCO with a FoM of 190.4 dBc/Hz at 1 MHz offset frequency and a 1/f(3) PN corner frequency of 300 kHz across the frequency tuning range from 5.2 GHz to 6.1 GHz, the RS-PLL prototype fabricated in a 65-nm CMOS achieves low RMS jitter and REF spur of 64.8 fs and -84.1 dBc, respectively, while dissipating 6.9 mW, corresponding to a jitter-power FoM ( FoM(J )) of -255.4 dB.

关键词： Voltage-controlled oscillators Noise Jitter Capacitors Phase locked loops Power demand Detectors Very large scale integration Clocks Phase noise Gain-boosting phase detector jitter phase-locked loop phase noise reference-sampling reference spur

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An LBM study of multichannel flow boiling for electronic thermal management coupling flow instability mitigation

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APPLIED THERMAL ENGINEERING 2024年 239卷

作者： Chen, Jingtan Shi, Dan Khan, Shahid Ali Dong, Kejian Mousa, Abd Allah A. Zhao, Jiyun City Univ Hong Kong Dept Mech Engn Kowloon Tong Tat Chee Ave Hong Kong Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau FST ECE Macau Peoples R China Taif Univ Coll Sci Dept Math & Stat POB 11099 Taif 21944 Saudi Arabia

The rising heat dissipation requirement on electronic devices urges a more efficient and energy-saving cooling strategy to keep the equipment operating within a safe temperature range. Multichannel flow boiling provides a straightforward solution to this challenge due to enormous latent energy of vapor preventing heat accumulation. However, pressure drop minimization and flow instability mitigation should also be considered for optimizing multichannel design. Hence, a Lattice Boltzmann Method (LBM) study on multichannel flow boiling process is conducted to provide design-based suggestions. The effects of surface wettability, channel number, input heat flux, and inlet velocity on the two-phase flow characteristics, heat transfer coefficient enhancement, dimensionless pressure drop, and flow instability are compared to examine the overall performance. Non-dimensional pressure drop is proposed for comparison through dividing the pressure drop under two-phase flow stage by the pressure drop under single-phase flow stage. Results show that hydrophilic coating prevents the film boiling transition at high input heat flux and reduces the maximum temperature for safer electronic operation. Designing a dense channel array can enhance the overall HTC but also significantly increase flow instability on the inlet, leading to shorter pumping operation life. A hybrid design of multichannel with downstream microgap region is proposed, and results indicate great mitigation ability with the increase of gap length and inlet velocity. These findings offer an invaluable blueprint for multichannel heat sink design and reveal the mechanisms of flow boiling enhancement.

关键词： Multichannel flow boiling Heat transfer enhancement Lattice Boltzmann Method Flow instability

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A SAW-less 3FLO-Suppression RF Transmitter with a Transformer-Based N-Path Switched-Capacitor Modulator Achieving -157.6dBc/Hz Output Noise and -61dBc CIM3

A SAW-less 3FLO-Suppression RF Transmitter with a Transforme...

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IEEE Symposium on Radio Frequency Integrated Circuits (RFIC)

作者： Gengzhen Qi Haonan Guo Pui-In Mak Yunchu Li School of Microelectronics Science and Technology Sun Yat-Sen University China State-Key Lab. of Analog and Mixed-Signal VLSI/IME and FST-ECE University of Macau China

ISBN: (数字)9798350359473

ISBN: (纸本)9798350359480

This paper reports a SAW-less RF transmitter with a passive-intensive I/Q modulator. Specifically, without the noisy and nonlinear transconductor (g m ), our proposed linear I/Q modulator features a transformer-based N-path switched-capacitor (SC) topology to enable high-Q bandpass filtering at a flexible RF, rejecting the out-of-band (OB) noises in baseband (BB) and the modulator. The intrinsic lowpass characteristic of the transformer also reduces the harmonic terms at 3xf LO at the output of the modulator, thereby effectively suppressing CIM 3 . For the power amplifier (PA) driver, it is aided by a paralleled-g m linearizer to improve the performance. Prototyped in a 65nm CMOS process, our transmitter manifests a consistently low OB noise (≤-157dBc/Hz) for 2 to 3GHz. Under a 2.3dBm output power, the transmitter shows a high transmitter efficiency (5.1%) and a high linearity (CIM 3 <-60dBc and ACLR 1 <-46dBc). The power consumption is 32.5mW at 2.5GHz, and the active area is 0.21mm 2 .

关键词： Radio frequency Radio transmitters Noise Modulation Power amplifiers Linearity Switches

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A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第2期71卷 689-702页

作者： Wu, Hao Chen, Yong Yuan, Yiyang Yue, Jinshan Fu, Xiangqu Ren, Qirui Luo, Qing Mak, Pui-In Wang, Xinghua Zhang, Feng Chinese Acad Sci Inst Microelect Lab Microelect Device & Integrated Technol Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Integrated Circuit Beijing 100049 Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI & IME ECE Macau Peoples R China Beijing Inst Technol Sch Informat & Elect Beijing 100081 Peoples R China

Super-resolution (SR) task using the convolutional neural network is a crucial task in improving image and video quality. The introduction of the residual block (RB) raises the depth of the algorithm to perform better reconstruction. The processing of the RB leads to a decrease in hardware utilization and frequent off-chip communications. It is hard to apply such algorithms on edge devices with limited performance. Computing-in-memory (CiM) is one promising method to reduce high power caused by massive data movement in multiply-accumulation computation. The algebraic sparsity (AS) is the structured sparsity (SS) optimization for imaging computing. However, it is an unsolved problem to simultaneously realize the texture sparsity (TS) of the image and the SS of the algorithm in the CiM scheme while maintaining high hardware utilization. Thus, we propose a CiM-based SR task accelerator. There are three key contributions: first, a texture-aware workflow and a dynamic grouping CiM engine can concurrently support TS coupling with AS. Second, a macro-level pipeline scheme together with two custom-sized CiM macros and a high reuse-rate Hadamard transformation circuit reaches 91% hardware utilization. Third, a novel weight update strategy is devised to reduce the performance loss induced by the weight updating. The accelerator prototype is fabricated in a 28-nm CMOS. It scores a 22.8-44.3-TOPS/W peak energy efficiency at the voltage supply of 0.54-1.1 V and the operating frequency of 50-200 MHz, indicating 1.8-6.8x higher compared to the state-of-the-art CiM processors.

关键词： CMOS super-resolution (SR) computing-in-memory (CiM) texture sparsity (TS) algebraic sparsity (AS) structured sparsity (SS) multiply-accumulation (MAC)

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A 1224 V-Input HV-LV-Separated Hybrid SC PoL Converter With 355 mWmm³ Power Density at 3 A Load Current and 15.2 mm³ Power Passives

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IEEE TRANSACTIONS ON POWER ELECTRONICS 2023年第12期38卷 15109-15114页

作者： Zhang, Xiongjie Ma, Qiaobo Zhao, Anyang Jiang, Yang Law, Man-Kay Jiang, Junmin Takamiya, Makoto Martins, Rui P. Mak, Pui-In Univ Macau State Key Lab Analog & Mixed Signal VLSI IME Macau 999078 Peoples R China Univ Macau Dept ECE FST Macau 999078 Peoples R China Southern Univ Sci & Technol Dept Elect & Elect Engn Shenzhen 518055 Peoples R China Univ Tokyo Inst Ind Sci Tokyo 1538505 Japan Univ Lisbon P-1649004 Lisbon Portugal

This letter presents a high-power-density point-of-load dc-dc converter for 12/24 V input applications, using the proposed high voltage-low voltage separated hybrid switched-capacitor (SC) topology. By incorporating inductors between the SCnetworks in HV/LVdomains, the design achieves reduced inductor dc current (I-L,I- DC) at small voltage conversion ratios (VCRs), optimized switching and conduction losses, and extended duty ratio range, enabling the use of small-sized inductors with higher dc resistance and resulting in a compact system volume. LV switches handle most of the current conduction, reducing switching losses and silicon area for higher on-chip power density. The fabricated converter, using a 180-nm BCD process, generates 0.8-1.8 V output from 12/24 V inputs with a 3-A maximum load. Measured results show total I-L,I- DC of 1.2 A at VCR 0.075 and 2 A load. The converter achieves a peak power density of 355mW/mm(3) with a power passive volume of 15.2 mm(3). Peak efficiencies are 85% at 12 V input and 84.2% at 24 V input.

关键词： DC-DC high step-down hybrid inductor current reduction power density switched-capacitor (SC)

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