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Fully Symmetrical Obfuscated Interconnection and Weak-PUF-Assisted Challenge Obfuscation Strong PUFs Against Machine-Learning Modeling Attacks

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IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY 2024年 19卷 3927-3942页

作者： Xu, Chongyao Zhang, Litao Mak, Pui-In Martins, Rui P. Law, Man-Kay Univ Macau Inst Microelect Fac Sci & Technol FST ECE State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Fac Sci & Technol FST ECE Dept Elect & Comp Engn Macau Peoples R China Univ Macau Fac Sci & Technol FST ECE Dept State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China

In this paper, we propose a fully symmetrical obfuscated-interconnection PUF (SOI PUF), which contains n delay stages with each stage having 4k obfuscated interconnections for resisting machine learning (ML)-based modeling attacks. All the delay stages contribute to k PUF primitives while achieving a 20x increase in the number of possible interconnections with the same hardware resources over similar prior arts. The SOI PUF mathematical model also theoretically demonstrates the large number of nonlinear matrix multiplications for resisting ML-based modeling attacks. We further exploit parallel weak PUF cells and propose the challenge-obfuscated SOI PUF (cSOI PUF), which can effectively prevent adversaries from bypassing unknown interconnections through reverse engineering (RE) attacks. The proposed SOI PUF and cSOI PUFs are evaluated by both software simulation and FPGA measurements. Without requiring a large k as in the existing PUF architectures, the simulation results demonstrate that the proposed SOI and cSOI PUFs can achieve a similar to 50% prediction accuracy for k >= 3, even when facing ML attacks using 5-hidden-layer Artificial Neural Network (ANN) with 40M training CRPs. Furthermore, the proposed (64,2/4/6/8)-SOI PUF and (64,2/4/6/8)-cSOI PUF implemented using Xilinx Artix-7 FPGA can both achieve a measured reliability and uniformity of >94% and similar to 50%, respectively. Depending on the value of k , the uniqueness ranges from 29.1% to 42.7% for SOI PUFs, and further improves to similar to 50% for cSOI PUFs. The resilience against reliabiltiy-based modeling attacks, Probably Approximately Correct (PAC) attacks and RE-based modeling attacks will also be discussed.

关键词： Physical unclonable function (PUF) machine learning (ML) modeling attack symmetrical obfuscated interconnection (SOI) challenge obfuscation reverse engineering (RE)

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A VCF-Step-Reconfigurable Continuously Scalable-Conversion-Ratio Switched-Capacitor Converter

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IEEE JOURNAL OF SOLID-state CIRCUITS 2025年第2期60卷 626-637页

作者： Wang, Yuanfei Huang, Mo Chen, Qiujin Martins, Rui P. Lu, Yan Univ Macau Dept Elect & Comp Engn ECE State Key Lab Analog & Mixed Signal VLSI Fac Sci & Technol FSTInst Microelect Macau Peoples R China

This article proposes a V-CF -step-reconfigurable continuously scalable-conversion-reconfigurable CSC (RCSC). We first analyze the working principle of the conventional conversion-ratio SC (CSC) converter and why it has reduced efficiency over a wide voltage conversion ratio (VCR) range. Then, the proposed RCSC reconfigures and thus equalizes the step size of the flying capacitor C-F voltage (V-CF) according to the VCR. This maximizes efficiency over a wider range of VCRs, with limited circuitry complexity. Subsequently, we propose a gate control signal generation scheme that significantly reduces the cost overhead of the reconfiguration. The proposed RCSC can be used in either step-up or step-down mode and is compatible with maximum power point tracking (MPPT) in energy harvesting systems. Implemented with a 65-nm CMOS process, the proposed RCSC reaches a 90% peak efficiency using 34 V-CF steps and the widest normalized VCR range with > 75% efficiency.

关键词： Continuously scalable-conversion-ratio maximum power point tracking (MPPT) reconfigurable VCF step switched-capacitor (SC) converter wide voltage conversion ratio (VCR) range

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Recent advancements in continuously scalable conversion-ratio switched-capacitor converter

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Journal of Semiconductors 2024年第4期45卷 8-11页

作者： Mo Huang Yuanfei Wang Rui P.Martins Yan Lu State Key Laboratory of Analog and Mixed-Signal VLSI Institute of MicroelectronicsUniversity of MacaoMacaoChina

Switched-capacitor(SC)DC-DC converter[1]is an impor-tant alternative to inductive DC-DC converter,in terms of removing the bulky power ***,it is widely used in low-profile,low-power applications,such as the internet of things(IoT)sensor nodes and energy harvesting[2].Mean-while,considering that capacitor has a much higher energy density than inductor,high-power applications.

关键词： converter switched removing

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A 12-/13.56-MHz Crystal Oscillator With Binary-Search-Assisted Two-Step Injection Achieving 5.0-nJ Startup Energy and 45.8-μs Startup Time

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IEEE JOURNAL OF SOLID-state CIRCUITS 2024年第2期59卷 464-475页

作者： Li, Haihua Lei, Ka-Meng Martins, Rui P. Mak, Pui-In Univ Macau Fac Sci & Technol Elect & Comp Engn ECE State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Fac Sci & Technol Elect & Comp Engn ECE State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China

This article reports a 12-/13.56-MHz fast-and-energy-efficient startup crystal oscillator (XO) featuring a binary-search-assisted two-step injection technique for ultralow-power duty-cycled radios. Specifically, after the first injection, a calibration module refines the auxiliary oscillator's frequency toward the crystal's resonant frequency in a binary-search fashion with a sub-500-ppm error for the second injection. This calibration method eliminates the closed-loop phase-locked loop (PLL) and shortens the calibration period into 48 clock cycles. Prototyped in a 65-nm CMOS process, the XO occupies an active area of 0.134 mm(2). The 13.56-MHz XO can achieve a startup time (t(s)) of 45.8 mu s with a V-DD of 0.7 V, while consuming 5.0 nJ of energy. t(s) varies by +/- 2.2% amid temperature variations (-40 degrees C to 85 degrees C). Its steady-state power consumption is 28.4 mu W, with an output phase noise of -143.7 dBc/Hz at 1-kHz offset (FoM: 241.8 dBc/Hz), manifesting its state-of-the-art performance.

关键词： Binary-search algorithm crystal oscillator (XO) Internet-of-Things (IoT) ring oscillator sandwich capaci-tor stepwise injection two-step injection ultralow power (ULP)

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A 320MHz BW NS TD-ADC Assisted C/DT Hybrid Pipelined ADC with SAB-based Residue Amplifying Filter

A 320MHz BW NS TD-ADC Assisted C/DT Hybrid Pipelined ADC wit...

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2024 IEEE Asian Solid-state Circuits Conference, A-SSCC 2024

作者： Xing, Kai Zhu, Yan Martins, Rui Paulo Chan, Chi-Hang State-Key Laboratory of Analog and Mixed Signal VLSI DECE FST University of Macau China

ISBN: (纸本)9798350376326

With the advent of WLAN technologies, over 320 MHz BW and > 65dB DR ADCs become indispensable to support newly developed WiFi standards. Three classic solutions can reach the said targets but involve various compromises (Fig. 1 top). CT MASH ADCs [1] rely on a relatively high OSR (7) as well as NS order to accommodate the adequate noise spectral density (NSD), limiting the energy efficiency. The CT pipeline (PIPE) ADC [2-3] obviates the feedback loop and its 1st stage energy effectively provides preliminary quantization, residue generation, amplification, and filtering. However, the backend CT quantization can be power-hungry [2] [4]. The DT NS pipeline ADC offers a low-power alternative [5] but loses the intrinsic anti-aliasing (AA) ability from its CT counterparts. This work hybridizes CT and DT NS PIPE, gaining the pros from the CT PIPE front-end and DT PIPE backend. Together with the Single amplifier biquad (SAB) - Residue Amplifying Filter (RAF) and NS TD-QTZ, the C/DT PIPE ADC demonstrates superior energy efficiency over CT MASH ADCs with 320MHz BW. © 2024 IEEE.

关键词： Anti-aliasing

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Characterization and Modeling of MOSFET Series Resistance Down to 4 K

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IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY 2025年 13卷 297-302页

作者： Lin, Yuhuan Ma, Zhizhao Li, Shilong Wen, Tianyue Zhou, Yuxuan Su, Hao Zhou, Shenghua Lin, Longyang Li, Yida Chen, Kai Southern Univ Sci & Technol Sch Microelect Shenzhen 518055 Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI IME ECE FST Macau Macao Peoples R China

MOSFET parasitic series resistance (R-SD) is an important parameter when channel length scales down. This paper presents a systematic study of R-SD extracted from the mobility constant method down to 4 K. For the first time, the anomalous behavior of R-SD with temperature lowering is interpreted and modeled by combined effects of dopant freeze-out and mobility. Excellent fit between the standard N/P-MOSFET measurement data and this model for 40 nm bulk device from leading foundry is shown from 300 K to 4 K. In addition, R-SD change with width scaling combined with temperature effects is also discussed.

关键词： Resistance MOSFET circuits Logic gates MOSFET Semiconductor device modeling Junctions Electrical resistance measurement Cryogenics Conductivity Systematics Series resistance R-SD cryogenic extraction model

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A 27 W Wireless Power Transceiver With Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control

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IEEE JOURNAL OF SOLID-state CIRCUITS 2024年第6期59卷 1782-1793页

作者： Ma, Xiaofei Ki, Wing-Hung Lu, Yan Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Hong Kong Peoples R China Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Fac Sci & Technol FST ECE Macau Peoples R China Univ Macau Fac Sci & Technol FST ECE Dept Elect & Comp Engn Macau Peoples R China

This work presents a reconfigurable single-stage regulated Class-E (SSRE) wireless power transceiver that delivers 27 W for wireless charging at 6.78 MHz. The power stage of the transmitter merges a buck and a Class-E power amplifier (PA) into one conversion stage, saving one inductor and one capacitor with improved system efficiency. Instead of using a bulky external impedance tuning block to ensure a 50% duty cycle operating point, the proposed Class-E zero-voltage switching (ZVS) controller allows the Class-E stage to work at an adaptive duty cycle without an off-chip tuning circuit. The high voltage and high current stress of the Class-E stage is handled by a GaN transistor, the driver of which uses an NMOS transistor for the high-side switch that realizes a rising edge of 2.8 ns with no overshoot. For directly sensing high voltage without using a resistor divider, an HV-NMOS shielded push-pull comparator is designed. An adaptive dead time control based on a sample-and-hold (S/H) feedback loop is proposed to reduce reverse conduction and recovery loss of the buck stage. The proposed solution demonstrates good trade-off among power level, efficiency, and power density. The SSRE WPT system delivers a maximum dc output power of 27 W with an end-to-end (E2E) efficiency of 63.0% if the receiver uses a traditional passive rectifier. The peak E2E efficiency of 80.0% is achieved at dc output power of 9.5 W;furthermore, in a two-chip differential transmitter configuration, the maximum output power reaches 45 W, and the maximum E2E efficiency is 83.7%.

关键词： AC-DC adaptive dead time dc-ac device-to device (D2D) GaN driver power amplifier (PA) rectifier single stage regulation wireless fast charging wireless power transfer zero-voltage switching (ZVS)

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Reactive oxygen species and nitric oxide scavenging nanoparticles alleviating rheumatoid arthritis through adjusting the seeds and growing soils

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Acta Pharmaceutica Sinica B 2023年第12期13卷 5016-5029页

作者： Peng Hua Ruifeng Liang Yanbei Tu Yuying Yin Man-Kay Law Meiwan Chen State Key Laboratory of Quality Research in Chinese Medicine Institute of Chinese Medical SciencesUniversity of MacaoMacao SARChina State Key Laboratory of Analog and Mixed-Signal VLSI IME and FST-ECEUniversity of MacaoMacao SARChina

Normalizing inflamed soils including reactive oxygen species(ROS),nitric oxide(NO),cellfree DNA,and regulating infammation-related seeds such as macrophages,neutrophils,fibroblasts,represent a promising strategy to maintain synovial tissue homeostasis for rheumatoid arthritis(RA)***,ROS scavenging amphiphilic block copolymer PEGylated bilirubin and NO-scavenging PEGylated o-phenylenediamine were fabricated to self-assemble into a dually responsive nanoparticle loaded with JAK inhibitor notopterol(Not@BR/oPDA-PEG,NBOP NPs).The simultaneous ROS and NO depletion combined with JAK-STAT pathway inhibition could not only promote M2 polarization to reduce further ROS and NO generation,but also decrease cytokines and chemokines to prevent immune cell ***,NBOP NPs responded to high level ROS and NO,and disintegrated to release notopterol in inflamed joints as the hydrophobic heads BR and oPDA were transformed into hydrophilic *** released notopterol could inhibit the JAK-STAT pathway of infammatory cells to reduce the secretion of pro-inflammatory cytokines and *** strategy represented an effective way to regulate RA soils and seeds through breaking the positive feedback loop of inflammation aggravation,achieving an excellent anti-RA efficacy in a collagen-induced arthritis rat *** together,our work offered a reference to adjust RA soils and seeds for enhanced RA treatment.

关键词： Bilirubin o-Phenylenediamine Notopterol ROS and NO scavenging JAK-STATpathway Anti-inflammatory Cartilage protection Rheumatoid arthritis

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High-Efficiency Ultrasound Energy Harvesting Interface With Auto-Calibrated Timing Control From-25 ^°C to 85 ^°C

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IEEE JOURNAL OF SOLID-state CIRCUITS 2025年第3期60卷 871-882页

作者： Zhao, Guangshu Xie, Chao Wang, Chenxi Zhang, Milin Law, Man-Kay Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau FST ECE Macau Peoples R China Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China

This work presents a high-efficiency ultrasound energy harvesting interface with auto-calibrated timing control, featuring: 1) the proposed C(P )auto-calibration, consisting of the half bias-flip time ( t(half) ) detection and adaptive closed-loop time calibration (ACTC) to improve the system's robustness against piezoelectric transducer (PZT) materials and environmental variations;2) the proposed charge recycling (CR) bootstrapping driver to reduce conduction loss and improve the C(P )auto-calibration accuracy as well as the peak voltage flipping efficiency ( eta flip );and 3) the proposed coarse detection and fine calibration technique to eliminate the inherent timing offset and increase the acceptable input excitation frequency range. The fabricated chip prototype in 0.18- mu m silicon on insulator (SOI) CMOS process can adapt to both PZT5A (nominal C-P similar to 114 pF) and PZT5H (nominal C-P similar to 190 pF) and is capable of operating over a wide temperature range from - 25 degrees C to 85 degrees C. The proposed C(P )auto-calibration and CR bootstrapping driver can improve the eta flip to as high as 93.6% at an output power of 496.6 mu W. With the proposed coarse detection and fine calibration technique, this work demonstrates a high measured peak power conversion efficiency (PCE) of 94.5%, corresponding to a similar to 23% improvement when compared with the prior ultrasound energy harvesting interface while achieving a favorable figure of merit (FoM) of 8.13 x

关键词： Ultrasonic imaging Timing Lead zirconate titanate Rectifiers Energy harvesting Power generation Calibration Temperature measurement Delays Accuracy Adaptive time control auto-calibration bias-flip interface energy harvesting high efficiency piezoelectric transducer (PZT) ultrasound

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A 24-V-Input Highly Integrated Interleaved-Inductor Multiple Step-Down Hybrid DC-DC Converter With Inherent Current Equalization Characteristics

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IEEE JOURNAL OF SOLID-state CIRCUITS 2024年第9期59卷 2895-2906页

作者： Zhang, Xiongjie Zhao, Anyang Ma, Qiaobo Jiang, Yang Law, Man-Kay Martins, Rui P. Mak, Pui-In Univ Macau Inst Microelect IME State Key Lab Analog & Mixed Signal VLSI Fac Sci & Technol FST Taipa Macau Peoples R China Univ Macau Fac Sci & Technol FST Dept ECE Taipa Macau Peoples R China

This article presents a highly integrated hybrid dc-dc converter with a 24-V input, employing the interleaved-inductor multiple step-down (IL-MSD) topology. The proposed design ensures symmetric power-stage operations, addressing inductor current ( I-L) imbalance without complex regulation control. It also optimizes current distribution among internal conduction branches, reducing conduction losses and input capacitor requirements. In addition, we propose an on-chip gate-driving scheme utilizing a high-voltage (HV) floating current (HVFC) source and HV charge storage technique, eliminating external bootstrap capacitors and extra HV supplies. Fabricated in a 180-nm BCD process, the converter chip integrates all-N-type power switches, gate drivers (GDs), startup/pre-charge circuits, and control blocks within a 4.7-mm $<^>{2}$ footprint. Using two 1- $\mu$ H compact inductors and four 1- $\mu$ F flying capacitors, the converter regulated a 1-3.5-V output from a 24-V input with a peak efficiency of 90.4% under a 1.2-A load. The maximum load current reaches 5 A with an 82% efficiency. The achieved on-chip and overall power densities are 3.51 and 0.62 W/mm(3) , respectively.

关键词： Switches Topology Inductors Video recording Power system measurements Density measurement Capacitors DC-DC converter fully symmetric high step-down hybrid topology interleaved inductor on-chip gate driver (GD)

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