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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Ran Zhang Ka-Fai Un Mingqiang Guo Liang Qi Dengke Xu Weibing Zhao R.P. Martins Franco Maloberti Sai-Weng Sin State-Key Laboratory of Analog and Mixed-Signal VLSI/Institute of Microelectronics-IME University of Macau Macao China Zhuhai UM Science and Technology Research Institute Zhuhai China Department of Micro-Nano Electronics Shanghai Jiao Tong University Shanghai China Amicro Semiconductor Company Zhuhai China On Leave From Instituto Superior Técnico/Universidade de Lisboa Portugal University of Pavia Pavia Italy

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

Many applications of machine learning (ML) have been integrated into edge devices with their low communication latency. In edge computation, the reprocessing of redundant data results in considerable energy waste. The prior research utilized a digital-delta-digital-sigma computing-in-memory (CIM) scheme to mitigate this redundancy. However, the 7-bit LSB-first ADC resulting from the near-zero-mean output distribution led to excessive area and latency overhead. The following digital adder further induced power consumption and latency. We propose a digital-delta-analog-sigma CIM macro incorporating an analog sigma converter (SC) for edge computation, involving a switch-capacitor integrator with a floating inverter amplifier (FIA) and a quantizer. The increased analog swing of the sigma integrator leads to the expanded output distribution, thereby maintaining comparable accuracy with a relaxed quantizer resolution. The simulation demonstrates that our strategy contributes to a 57.5% reduction in latency, a resolution decrease of 2 bits, and better energy efficiency. These improvements can potentially enhance energy efficiency and computational speed in edge computation devices.

关键词： Power demand Energy resolution Redundancy Switches Machine learning In-memory computing Inverters

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A comparative study of digital low dropout regulators

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Journal of Semiconductors 2020年第11期41卷 52-60页

作者： Mo Huang Yan Lu Rui P.Martins State Key Laboratory of Analog and Mixed-Signal VLSI Institute of MicroelectronicsDECE/FSTUniversity of MacaoMacaoChina On leave from the Instituto Superior Técnico Universidade de LisboaLisbon1049-001Portugal

Granular power management in a power-efficient system on a chip(SoC)requires multiple integrated voltage regulators with a small area,process scalability,and low supply *** on-chip analog low-dropout regulators(ALDOs)can hardly meet these requirements,while digital LDOs(DLDOs)are good ***,the conventional DLDO,with synchronous control,has inherently slow transient response limited by the power-speed ***,it has a poor power supply rejection(PSR),because the fully turned-on power switches in DLDO are vulnerable to power supply *** this comparative study on DLDOs,first,we compare the pros and cons between ALDO and DLDO in ***,we summarize the recent DLDO advanced techniques for fast transient response and PSR ***,we discuss the design trends and possible directions of DLDO.

关键词： low dropout regulator(LDO) digital control fast transient response power supply rejection(PSR) integrated voltage regulator

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A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC

A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shapin...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Ke Li Sai-Weng Sin Liang Qi Weibing Zhao Guoxing Wang R.P. Martins State Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST University of Macau Macao China Department of Micro-Nano Electronics Shanghai Jiao Tong University Shanghai China Amicro Semiconductor Co. Ltd. Zhuhai China On leave from Instituto Superior Técnico Universidade de Lisboa Portugal

ISBN: (数字)9781665484855

ISBN: (纸本)9781665484862

This paper presents a hybrid CT/DT0-2 multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) with a passive noise-shaping successive approximation register (NSSAR) ADC as the $2^{\mathrm{n}\mathrm{d}}$ stage. The overall architecture is simple and robust. The front-end stage employs the continuous-time (CT) operation to perform coarse quantization and provide inherent anti-aliasing and easy driving. The back-end stage uses a second-order NS-SAR architecture, which excels at PVT robustness, power efficiency, and scaling friendliness. It also results in large relaxation of matching issues between the analog and the digital domains compared with conventional CT-MASH. Behavioral simulation results demonstrate the effectiveness and robustness of the proposed hybrid MASH architecture.

关键词： Multi-stage noise shaping Technological innovation Quantization (signal) Simulation Modulation Robustness Hybrid power systems

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On fully differential incremental ∆σ ADC with initial feedback zeroing and 1.5-bit feedback 52

On fully differential incremental ∆σ ADC with initial feed...

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52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020

作者： Wang, Bo Law, Man-Kay Bermak, Amine Division of Information and Computing Technology College of Science and Engineering Hamad Bin Khalifa University Doha Qatar State Key Laboratory of Analog and Mixed-Signal VLSI FST-ECE University of Macau China

ISBN: (纸本)9781728133201

This paper presents the time-domain analysis of a fully differential incremental ∆Σ modulator. Particularly, the influence of the bipolar feedback signal on the quantization noise of the modulator is analyzed, which is overlooked in most IDC designs. Based on the analysis, an initial feedback zeroing scheme is introduced to decrease the quantization noise of the modulator. Moreover, the maximum number of output codeword that can be produced by the modulator is mathematically derived. Following the derivation, a control scheme is proposed to achieve 1.5-bit effective feedback without changing the quantizer and D/A topology. By applying the initial feedback zeroing and 1.5-bit feedback technique, quantization noise of the 1st- and 2nd-order modulators analyzed in this paper can be decreased by 4×, with very minor modifications on the modulator's original digital controllers. © 2020 IEEE

关键词： Modulators

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A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第11期70卷 4271-4282页

作者： Chen, Sikai You, Mingyang Yang, Yunqi Jin, Ye Lin, Ziyi Li, Yihong Li, Leliang Li, Guike Xie, Yujun Zhang, Zhao Wang, Binhao Tang, Ningfeng Liu, Faju Fang, Zheyu Liu, Jian Wu, Nanjian Chen, Yong Liu, Liyuan Zhu, Ninghua Li, Ming Qi, Nan Chinese Acad Sci Inst Semicond State Key Lab Superlatt & Microstruct Beijing 100083 Peoples R China Univ Chinese Acad Sci Ctr Mat Sci & Optoelect Engn Beijing 100049 Peoples R China Chinese Acad Sci Inst Semicond State Key Lab Integrated Optoelect Beijing 100083 Peoples R China Univ Chinese Acad Sci Sch Elect Elect & Commun Engn Beijing 100049 Peoples R China Univ Chinese Acad Sci Ctr Mat Sci & Optoelect Engn Beijing 100190 Peoples R China Chinese Acad Sci Xian Inst Opt & Precis Mech State Key Lab Transient Opt & Photon Xian 710119 Peoples R China Univ Chinese Acad Sci Sch Future Technol Beijing 100049 Peoples R China State Key Lab Mobile Network & Mobile Multimedia T Shenzhen 518055 Peoples R China ZTE Corp Shenzhen 518057 Peoples R China Peking Univ Collaborat Innovat Ctr Quantum Matter Sch Phys State Key Lab Mesoscop Phys Beijing 100871 Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI Taipa 999078 Macau Peoples R China Univ Macau IME ECE FST Taipa 999078 Macau Peoples R China

This paper presents a 50-Gb/s optical receiver (ORX) chipset, consisting of a transimpedance amplifier (TIA) and a clock and data recovery (CDR) circuit in a 45-nm silicon-on-insulator CMOS. The proposed inverter-based TIA employs hybrid shunt-series peaking inductors to extend the bandwidth (BW). A baud-rate CDR is proposed to reduce the sampling phases and clocking power by half. To optimise the ORX for in-package integration, a compact-size digital loop is adopted in each channel, and the clock is recovered by phase interpolation from a shared reference. A complete optical-to-electrical (OE) link is built by integrating the proposed ORX with a high-speed Silicon Photonics (SiP) photodetector (PD). Measurements show that the proposed TIA has a transimpedance gain of 53 dB Omega and a BW of 27 GHz. By integrating it with the SiP PD, the OE front-end (PD+TIA) achieves an input sensitivity of -7.7 dBm at 50 Gb/s and BER<10(-12) . It features a power efficiency of 1.61 pJ/bit at a data rate of 64 Gb/s. The complete 50 Gb/s ORX achieves data recovery at a quarter rate of 12.5 Gb/s with an output jitter of 1.6 ps(rms), and has a 3.125 GHz clock with phase noise of -115.22 dBc/Hz at an offset frequency of 1 MHz.

关键词： Optical receiver silicon photonics chiplet optical I/O CMOS TIA CDR baud-rate multi-chip module (MCM)

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A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp

A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM wit...

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Symposium on vlsi Circuits

作者： Kai Xing Wei Wang Yan Zhu Chi-Hang Chan Rui Paulo Martins State-Key Laboratory of Analog and Mixed Signal VLSI IME and DECE/FST University of Macau Macao China On leave from Instituto Superior Tėcnico Universidade de Lisboa Portugal

ISBN: (数字)9781728199429

ISBN: (纸本)9781728199436

This paper presents a wideband and energy-efficient single-loop 3 rd order CTSDM enabled by an ELD-SAB-Merged integrator and a 3-stage opamp. We utilize only a single DAC and opamp to accomplish the ELD compensation in the SAB structure. While featuring a PSQ technique and a 1 st order NS-SAR, the 28nm prototype achieves a 74.4dB SNDR in a 50MHz BW and consumes 10.4mW with 171.2dB FoM S .

关键词： Modulation Topology Very large scale integration Wideband Gain Semiconductor device measurement

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A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS 15

A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incr...

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15th IEEE Asian Solid-state Circuits Conference (A-SSCC)

作者： Wang, Biao Sin, Sai-Weng U, Seng-Pan Maloberti, Franco Martins, R. P. Univ Macau IME DECE FST State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Synopsys Macau Ltd Macau Peoples R China Univ Pavia Pavia Italy

ISBN: (纸本)9781728151069

This paper presents a linear-exponential two-phase multi-bit incremental ADC (IADC). The exponential integration in the proposed IADC is generated by positively feedback the integrator output to the input, which can accumulate the signals stably due to the reset operation in IADC. To avoid the nonlinearity due to the signal-dependent charge injected from the reference, this work separates the sampling capacitor and the DAC capacitor. It will relax the requirement of reference buffer for fast-settling under a high sample rate. Then, we reconfigure the DAC capacitor to directly offer the exponential integration, resulting in saving in the usage of integration capacitor with a compact implementation. The linear-exponential two-phase scheme provides data-weighted-averaging-friendly weighting function to suppress the multi-bit DAC mismatch error. Fabricated in a 65nm CMOS under 1.2V supply and clocked at 128MHz, the ADC achieves an SNDR/DR/SFDR of 86.02/94.6/103.03dB with 500kHz BW, 20mW & 0.26mm(2), resulting in FoMs of 168.57dB.

关键词： Linear-exponential Multi-Bit Incremental ADC Data Weighted Averaging Positive Feedback

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A 10-Bit 200-kS/s 1.76-μW SAR ADC With Hybrid CAP-MOS DAC for Energy-Limited Applications

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2019年第5期66卷 1716-1727页

作者： Zhang, Hongshuai Zhang, Hong Song, Yan Zhang, Ruizhi Xi An Jiao Tong Univ Sch Elect & Informat Engn Xian 710049 Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI DECE FST Macau 999078 Peoples R China

This paper presents a low-power and area efficient 10-bit successive approximation register (SAR) analog-to-digital (ADC) with a hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC (MDAC), which consumes less power and much smaller chip area than a pure CDAC. Instead of using a string of eight MOS transistors to control one unit capacitor, the 3-bit LSB MDAC is realized by a MOS string with four native MOS transistors to control two unit capacitors, which allows higher voltage drop and more reliable operation for each unit MOS. The overall energy consumption of the proposed CAP-MOS DAC is reduced by 56.2% compared to a Vcm-based 10-bit pure CDAC with the same unit capacitance. Under the sampling rate of 200 kS/s, the prototype 10-bit SAR ADC implemented in a 0.18-mu m CMOS technology achieves a signal-to-noise-and-distortion ratio / spurious-free dynamic range of 56.91 /68.56 dB at 99-kHz input under a 0.6-V power-supply, while consumes 1.76 mu W at 200 kS/s for a figure of merit of 15.38 fJ/step. The peak DNL and INL are +0.27/-0.21 LSB and +0.43/-0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm(2).

关键词： analog to digital converter energy efficient mismatch noise area efficient low voltage hybrid CAP-MOS successive approximation register

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A-40-125 °C, 0.8 V, 33 kHz relaxation oscillator with integrated voltage and current reference and compensated comparator delay

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MICROELECTRONICS JOURNAL 2021年 117卷

作者： Wang, Lidan Zhan, Chenchang Zhang, Zhaobo Zhao, Shuangxing Southern Univ Sci & Technol SUSTech Sch Microelect Shenzhen 518055 Guangdong Peoples R China SUSTech Dept Elect & Elect Engn Univ Key Lab Adv Wireless Commun Guangdong Prov Shenzhen Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI IME FST ECE Macau 999078 Peoples R China

This paper presents a novel 33 kHz relaxation oscillator with temperature compensation over - 40-125 degrees C range. The voltage and current references are integrated within the proposed relaxation oscillator, and the resistor used to generate the voltage reference can be omitted. The reference voltage for the comparator input is temperature insensitive, and the temperature coefficient (TC) of the bias current is utilized to compensate the TC of the comparator delay. The proposed oscillator with integrated voltage and current reference and compensated comparator delay is fabricated in a 180-nm CMOS process with an active area of 0.057 mm2. The measured average TC of the output frequency is 96.1 ppm/degrees C for a temperature range of - 40-125 degrees C, and the line sensitivity is 2.6%/V for supply voltage of 0.8-2V. The power consumption is 97 nW when the supply voltage is 0.8V, and the frequency variation is +/- 0.7%.

关键词： -Relaxation oscillator Voltage and current reference Delay Temperature compensation

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A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing 33

A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR ...

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39th Symposium on vlsi Technology / 33rd Symposium on vlsi Circuits

作者： Guo, Minggiang Mao, Jiaji Sin, Sai-Weng Wei, Hegong Martins, R. P. Inst Microelect IME State Key Lab Analog & Mixed Signal VLSI Beijing Peoples R China Univ Macau DECE FST Macau Peoples R China Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9784863487185

This paper presents a 5GS/s 16-way Time-Interleaved SAR ADC in 28nm CMOS, proposing a fully-digital background timing-skew calibration based on digital mixing, without adding any extra analog circuits. We implement the sub channel SAR with a splitting-combined monotonic switching procedure. The prototype ADC achieves 48.5dB SNDR at Nyquist rate, while the power consumption is 29mW leading to a Walden FOM of 26.70/conv-step.

关键词： Calibration Timing Switches Frequency measurement Finite impulse response filters Very large scale integration Correlation

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