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A 0.003-mm² 440fsRMS-Jitter and-64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS 15

A 0.003-mm<SUP>2</SUP> 440fsRMS-Jitter and-64dBc-Reference-S...

引用

15th IEEE Asian Solid-state Circuits Conference (A-SSCC)

作者： Yang, Zunsong Chen, Yong Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME FST ECE Macau Peoples R China Univ Lisbon Inst Super Tecn Lisbon Portugal

ISBN: (纸本)9781728151069

This paper reports a current-reuse sampling phase detector for a type-I phase -locked loop (PLL) to simultaneously achieve both wide loop bandwidth and low control voltage ripple, resulting in low RMS jitter and reference spur, while minimizing the chip area by avoiding an explicit loop filter. Fabricated in 28nm CMOS, the PLL prototype measures a jitter of 440 fsRMs, and a spur level of -64 dBc at 3.296 GHz. The die area is 0.003 mm(2).

关键词： Ring voltage-controlled oscillator (VCO) phase locked loop (PLL) reference spur RMS jitter phase detector

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Compact Low-Loss LTCC Diplexer Using Lumped-Element Lowpass and Bandpass Filters for 2.4/5-GHz Application

Compact Low-Loss LTCC Diplexer Using Lumped-Element Lowpass ...

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IEEE International Workshop on Electromagnetics, Applications and Student Innovation (iWEM)

作者： Xulei Deng Jin-Xu Xu Xiu Yin Zhang Jingtao Zeng Kun Huang Shiwo Ta School of Electronic and Information Engineering South China University of Technology Guangzhou China State Key Laboratory of Analog and Mixed-Signal VLSI Institute of Microelectronics and FST-ECE University of Macau Macau China Pazhou Lab. Guangzhou China Guangdong Feng-hua Advanced Technology (Holding) Co. Ltd Zhaoqing China

ISBN: (纸本)9781665418294

This paper presents a low-temperature co-fired ceramic (LTCC) diplexer for 2.4/5-GHz applications. A simple schematic based on lumped-element lowpass and bandpass filters is proposed for realizing the diplexer. The lowpass filter is designed with a cut-off frequency of 3.7 GHz and three transmission zeros are generated to improve the out-of-band rejection. The bandpass filter is proposed with two transmission zeros locating at two sides of the passband. By using a complementary structure to combine the lowpass and bandpass filters, the LTCC diplexer is simulated with low insertion loss of smaller than 0.38 dB for 2.4 GHz application and 0.59-0.65 dB for 5-GHz application. The in-band isolation at the two operating bands are better than 20 dB, which is acceptable for many wireless applications. The presented LTCC diplexer has a circuit size is 1.0 × 0.5 × 0.35 mm 3 , which is very compact as compared to reported LTCC diplexers.

关键词： Band-pass filters Wireless communication Technological innovation Three-dimensional displays Conferences Cutoff frequency Insertion loss

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Multibit sturdy mash δσ modulator with error-shaped segmented dacs for wideband low-power applications 13

Multibit sturdy mash δσ modulator with error-shaped segmen...

引用

13th IEEE International Conference on ASIC, ASICON 2019

作者： Qi, Liang Sin, Sai-Weng Martins, Rui Paulo State-Key Laboratory of Analog and Mixed-Signal VLSI Institute of Microelectronics-IME University of Macau Department of ECE Faculty of Science and Technology China Instituto Superior Técnico Universidade de Lisboa Portugal

ISBN: (纸本)9781728107356

This paper presents several techniques to enhance the resolution of sturdy multi-stage noise shaping (MASH) ΔΣ modulator (DSM). The proposed structure significantly suppresses the quantization noise (QN) by employing a high-resolution quantizer with a segmented MSB/LSB DAC feedback in the first loop as well as noise coupling techniques in both loops. Reducing QN of the first loop significantly decreases the output swings of the integrators, thus improving the stability of the first loop. Besides, the construction of one extra order shaping function mitigates the leakage of coarse QN introduced by a gain mismatch between MSB and LSB DACs of the high-resolution quantizer. Simulation results demonstrate the effectiveness of the proposed architecture to achieve high resolution while employing low-gain op-amps for all integrators. © 2019 IEEE.

关键词： Modulators

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On Fully Differential Incremental ΔΣ ADC with Initial Feedback Zeroing and 1.5-Bit Feedback

On Fully Differential Incremental ΔΣ ADC with Initial Feed...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Bo Wang Man-Kay Law Amine Bermak Division of Information and Computing Technology College of Science and Engineering Hamad Bin Khalifa University Doha Qatar State Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE University of Macau Macau China

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

This paper presents the time-domain analysis of a fully differential incremental ΔΣ modulator. Particularly, the influence of the bipolar feedback signal on the quantization noise of the modulator is analyzed, which is overlooked in most IDC designs. Based on the analysis, an initial feedback zeroing scheme is introduced to decrease the quantization noise of the modulator. Moreover, the maximum number of output codeword that can be produced by the modulator is mathematically derived. Following the derivation, a control scheme is proposed to achieve 1.5-bit effective feedback without changing the quantizer and D/A topology. By applying the initial feedback zeroing and 1.5-bit feedback technique, quantization noise of the 1 st - and 2 nd -order modulators analyzed in this paper can be decreased by 4×, with very minor modifications on the modulator's original digital controllers.

关键词： Modulation Quantization (signal) Topology analog-digital conversion Time-domain analysis Digital-analog conversion Feedback control

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An N × N Multiplier-Based Multi-Bit Strong PUF using Path Delay Extraction

An N × N Multiplier-Based Multi-Bit Strong PUF using Path D...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Chongyao Xu Jieyun Zhang Man-Kay Law Xiaojin Zhao Pui-In Mak Rui P. Martins State Key Laboratory of Analog and Mixed-Signal VLSI IME and FST-ECE Universitm y of Macau Macao China College of Electronics and Information Engineering Shenzhen University Shenzhen China College of Electronics and Information Engineering Shenzhen University Shenzhen China Instituto Superior Técnico Universidade de Lisboa Portugal

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

This paper presents a digital N × N multiplier-based multi-bit strong physical unclonable function (PUF), which utilize the intrinsic path delay of the multiplier to achieve an approximated 1 : 2N 2 average challenge-to-response extraction to effectively increase the number of PUF responses. The PUF Extractor triggers the digital multiplier, and further processes the multiplier intrinsic path delay through a time-to-digital converter (TDC). Implemented with Xilinx Artix-7 FPGAs using the automatic place and route function, the proposed strong PUF demonstrates a 64-bit challenge with 32-bit multipliers with an extra level of unpredictability for counterfeiting model-based machine learning attack. With an average of 1:2048 responses per challenge, measurement results show that the uniqueness is 53.16%, and the stability of up to 95.54%, respectively.

关键词： Delays Field programmable gate arrays Stability analysis Circuit stability Digital circuits Hardware Clocks

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A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS

A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-V...

引用

IEEE Asian Conference on Solid-state Circuits (ASSCC)

作者： Zunsong Yang Yong Chen Pui-In Mak Rui P. Martins State Key Laboratory of Analog and Mixed-Signal VLSI and IME/FST-ECE University of Macau Macau China Instituto Superior Técnico Universidade de Lisboa Portugal

ISBN: (数字)9781728151069

ISBN: (纸本)9781728151076

This paper reports a current-reuse sampling phase detector for a type-I phase-locked loop (PLL) to simultaneously achieve both wide loop bandwidth and low control voltage ripple, resulting in low RMS jitter and reference spur, while minimizing the chip area by avoiding an explicit loop filter. Fabricated in 28-nm CMOS, the PLL prototype measures a jitter of 440 fs RMS , and a spur level of -64 dBc at 3.296 GHz. The die area is 0.003 mm 2 .

关键词： Phase locked loops Voltage-controlled oscillators Jitter Latches Switches Detectors Capacitors

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A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS

A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) ...

引用

IEEE Asia-Pacific Conference on Circuits and Systems

作者： Xiaoteng Zhao Yong Chen Pui-In Mak Rui P. Martins State Key Laboratory of Analog and Mixed-Signal VLSI and IME/FST-ECE University of Macau Macao China Instituto Superior Técnico Universidade de Lisboa Portugal

This paper reports a trimodal (NRZ/PAM-4/PAM-8) half-rate bang-bang clock and data recovery (BBCDR) circuit featuring single-loop phase tracking, and low-power techniques at both the architecture and circuit levels to improve the overall energy efficiency. Fabricated in 28-nm CMOS, the prototype achieves a 0.29/0.17/0.14 pJ/bit efficiency at 14.4/28.8/43.2 Gb/s in NRZ/PAM-4/PAM-8 modes, respectively. The integrated jitter is PP jitter tolerance is achieved up to 10 Mhz for all the three modes.

关键词： Clocks Jitter Decoding Optical signal processing Tracking loops Generators Voltage-controlled oscillators

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A 17.7-pJ/Cycle ECG Processor for Arrhythmia Detection with High Immunity to Power Line Interference and Baseline Drift

A 17.7-pJ/Cycle ECG Processor for Arrhythmia Detection with ...

引用

IEEE Asian Conference on Solid-state Circuits (ASSCC)

作者： Yue Yin Syed Muhammad Abubakar Songyao Tan Hanjun Jiang Zhihua Wang Seng-Pan U Wen Jia Tsinghua Beijing Innovation Center for Future Chips Inst. of Microelectronics Tsinghua Univ. Beijing China Guangdong Engr. Research Center on ICs for Wireless Healthcare Research Inst. of Tsinghua Univ. Shenzhen China State-Key Laboratory of Analog and Mixed-Signal VLSI IME/ECE/FST Univ. of Macau Macao China

ISBN: (数字)9781728184364

ISBN: (纸本)9781728184371

A full-customized electrocardiograph (ECG) processor for arrhythmia detection is proposed in this paper, which is composed of detection engine, circulated buffer, register bank and instruction/data interfaces. The processor, which is fed by 0.9-V parallel digitized ECG signals, generates stamp pulses of detected QRS-complexes and arrhythmia location by searching for local extremes of signal derivative with self-adaptive thresholds. The precision (Pre) and sensitivity (Sen) of the proposed algorithm are 99.1% and 96.9% respectively. The extra false positive (FP) rate of proposed ASIC-implemented ECG processor is extremely low even with power-line interference (PLI) of 0.0663 Vp and/or rail-to-rail baseline drift (R2R BLD). The processor stands out for its relatively low power consumption of 17.7 pJ/cycle with superior robustness to interferences compared to other designs in literature.

关键词： Sensitivity Power demand Interference Electrocardiography Robustness Solid state circuits Registers

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Digital Battery Management Unit with Built-In Resistance Compensation and Accidental Mutation Protection for Fast and Accurate Charging

Digital Battery Management Unit with Built-In Resistance Com...

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IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)

作者： Ji-Xuan Li Sai-Weng Sin U-Fat Chio Ya-Jie Wu Chi-Seng Lam Rui Paulo Martins State-Key Laboratory of Analog and Mixed-Signal VLSI IME/ECE/FST University of Macau Macau China Instituto Superior Técnico/Universidade de Lisboa Lisbon Portugal

ISBN: (数字)9781728150406

ISBN: (纸本)9781728150413

This paper proposes a digital battery management unit (BMU) with built-in resistance (BIR) compensation and accidental mutation protection (AMP) techniques to achieve fast and accurate charging, which applied in LDO-based charger. The digital compensation dynamically estimates the BIR. The battery can get fully charged with large rated charging current in pulsed constant current (PCC) mode and effectively reduced the charging time. AMP calibrates the mutate messages automatically to deal with some unexpected situations and guarantee the steady operation for the compensation module. The BMU is fabricated in 28 nm CMOS, occupies 0.014 mm 2 of silicon area. Experimental results show that 73.3% charging time is reduced with 1.5A charging current. The power consumption of the digital chip is 59.1 μW.

关键词： Resistance Semiconductor device measurement Lithium-ion batteries Adders Reliability Timing

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A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS

A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hyb...

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IEEE Asia-Pacific Conference on Circuits and Systems

作者： Arya Balachandran Yong Chen Chirn Chye Boon Nanyang Technological University Singapore Singapore State Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE University of Macau Macau China

A 32-Gb/s adaptive receiver analog front-end (AFE) with a hybrid continuous-time linear equalizer (CTLE), a half-rate distributed edge and data decision feedback equalizer (DFE) and a clock data recovery (CDR) is presented. The hybrid CTLE counters the low-frequency as well as the high-frequency loss of 21 dB at Nyquist. Further post-cursors can be solved by using a half- rate, distributed 3-tap edge-DFE and 2-tap data-DFE, which is partially embedded in the CDR. The distributed DFE scheme addresses the inter symbol interference (ISI) at the edge and reduces the data jitter while data-DFE guarantees the vertical opening of the data eye. Fabricated in 65-nm CMOS, occupying an active area of 0.3 mm 2 , the proposed prototype demonstrates an improvement of 0.15 UI in the horizontal eye opening of the data output at a receiver AFE with the conventional 5-tap data-DFE at BER=10 -12 , under a pseudorandom binary sequence (PRBS) of 2 31 -1. The competitive power efficiency of 3.53 mW/Gb/s is measured with a supply voltage of 1.2 V.

关键词： Decision feedback equalizers Receivers Clocks Jitter Timing Loss measurement Distributed databases

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