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A 2- $\mu\text{W}$ 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop

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IEEE Transactions on Circuits and Systems II: Express Briefs 2016年第4期63卷 351-355页

作者： Jiangchao Wu Man-Kay Law Pui-In Mak Rui P. Martins State Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECEA University of Macau Macao China State Key Laboratory of Analog and Mixed-Signal VLSI University of Macau Macao China State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE Instituto Superior Técnico /Universidade de Lisboa Portugal Lisboa Portugal

This brief presents an ultra-low-power low-noise chopped capacitively coupled instrumentation amplifier (CCIA) that is suitable for neural recording applications. An active high-pass filter is embedded in the ripple reduction loop (RRL) to suppress the residual noise and relax the capacitor size. Multiple chopping is employed to further reduce the residual output ripple due to the RRL offsets. A dc servo loop (DSL) using a 14-nA pseudofeedback amplifier is proposed to achieve a subhertz high-pass corner while using only a 15-pF on-chip capacitor. The complete CCIA is implemented in a standard 0.18-μm CMOS process. It occupies an area of 0.23 mm 2 (including the DSL) and consumes 1.7 μA from a 1.25-V supply, achieving a noise efficiency factor of 2.9 that compares favorably with the state of the art.

关键词： DSL Capacitors Loading Active filters Impedance Servomotors Power demand

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A high resolution multi-bit incremental converter insensitive to DAC mismatch error 12

A high resolution multi-bit incremental converter insensitiv...

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12th Conference on Ph.D. Research in Microelectronics and Electronics, PRime 2016

作者： Wang, Biao Sin, Sai-Weng Martins, R.P. State-Key Laboratory of Analog and Mixed Signal VLSI Dept. of ECE FST University of Macau China Synopsys Macau Ltd China Instituto Superior Técnico Universidade de Lisboa Portugal

ISBN: (纸本)9781509004935

This paper presents a second order multi-bit incremental analog-to-digital converter with two-phase feedback DAC control logic, insensitive to capacitor mismatches and with enhanced performance in multi-bit implementation. Besides, the proposed technique eliminates the complexity of dynamic element matching and relaxes the Op-amp's settling time. Behavioral simulations show that it can achieve 115.55 dB SNDR at 128 clock cycles using a 7-bit quantizer without dynamic element matching. © 2016 IEEE.

关键词： Operational amplifiers

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Sub-µW QRS detection processor using quadratic spline wavelet transform and maxima modulus pair recognition for power-efficient wireless arrhythmia monitoring

Sub-µW QRS detection processor using quadratic spline wavel...

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Asia and South Pacific Design Automation Conference

作者： Chio-In Ieong Pui-In Mak Mang-I Vai Rui P. Martins State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE University of Macau Macao China Instituto Superior Técnico Universidade de Lisboa Portugal

This paper describes a power-efficient processor for extracting the timing of QRS complex from digitized ECG, based on the hardware-efficient architecture of quadratic spline wavelet transform (QSWT) and maxima modulu... 详细信息

关键词： Wireless communication Electrocardiography Wireless sensor networks Wavelet transforms Timing Process control

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Time-domain I/Q-LOFT compensator using a simple envelope detector for a sub-GHz IEEE 802.11af WLAN transmitter

Time-domain I/Q-LOFT compensator using a simple envelope det...

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Asia and South Pacific Design Automation Conference

作者： Chak-Fong Cheang Ka-Fai Un Pui-In Mak Rui P. Martins State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE University of Macau Macao China On leave from Instituto Superior Técnico Universidade de Lisboa Portugal

ISBN: (纸本)9781467395700

This paper proposes a hardware-efficient time-domain scheme to digitally compensate the I/Q imbalance and LO feedthrough (LOFT) of a sub-GHz wideband transmitter for the IEEE 802.11af WLAN. A simple envelope detector is the only analog part. The parameters are updated by Least-Mean-Square and estimated efficiently in time domain by using COordinate Rotation DIgital Computer (CORDIC), saving the training time and power consumption. The measured wideband image-rejection ratio (IRR) and LO-leakage-rejection ratio (LRR) are improved from 18.9 to 41.3 dB, and 20.4 to 37.9 dB, respectively.

关键词： Calibration Time-domain analysis Wideband Transmitters Training Wireless LAN Envelope detectors

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A high-Q spiral inductor with dual-layer patterned floating shield in a class-B VCO achieving a 190.5-dBc/Hz FoM

A high-Q spiral inductor with dual-layer patterned floating ...

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International Symposium on Circuits and Systems

作者： Chee-Cheow Lim Harikrishnan Ramiah Jun Yin Pui-In Mak Rui P. Martins Department of Electrical Engineering Faculty of Engineering University of Malaya 50603 Kuala Lumpur Malaysia State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE University of Macau Macao China

ISBN: (纸本)9781479953424

This paper proposes a dual-layer patterned floating shield (DL-PFS) technique for Silicon-based on-chip spiral inductors. By optimally utilizing the two lowest metal layer strips to shield the inductor from the substrate, electromagnetic (EM) simulations show 40% improvement of the Q factor when compared with the conventional approach. Designed and simulated in 0.13-μm CMOS, the DL-PFS inductor in a class-B VCO achieves 6.6-dB lower phase noise, and 34% power savings. The VCO also exhibits 9.7-to-10.93 GHz tunability, and -123-dBc/Hz phase noise at a 3 MHz offset. The power consumption is 1.64 mW at 0.6 V, leading to a state-of-the-art FoM of 190.5 dBc/Hz.

关键词： Dual-layer Patterned Floating Shield Inductor RFIC VCO

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A 1.1 $\mu \text{W}$ CMOS Smart Temperature Sensor With an Inaccuracy of ±0.2 °C (${3}\sigma )$ for Clinical Temperature Monitoring

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IEEE Sensors Journal 2016年第8期16卷 2272-2281页

作者： Man-Kay Law Sanfeng Lu Tao Wu Amine Bermak Pui-In Mak Rui P. Martins State Key Laboratory of Analog and Mixed-Signal VLSI University of Macau Macao China State Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE University of Macau Macao Huada Empyrean Software Company Ltd. Beijing China College of Science and Engineering Hamad Bin Khalifa University Doha Qatar Department of Electronics and Computer Engineering Hong Kong University of Science and Technology Hong Kong Instituto Superior Técnico Universidade de Lisboa Lisbon Portugal

In this paper, an ultra-low power, high accuracy CMOS smart temperature sensor customized for clinical temperature monitoring based on substrate p-n-p bipolar junction transistors (BJTs) is presented. A power efficient analog front end with a sensing-range customized multi-ratio pregain stage is proposed to effectively utilize the input range of the incremental analog-to-digital converter to relax the conversion speed and resolution requirement. A block-based data weighted averaging technique is also proposed to achieve highly accurate pre-gain ratios while significantly reducing the implementation complexity. The complete temperature sensor is implemented in a standard 0.18 μm CMOS process occupying an active area of 0.198 mm 2 . Measurement results from 20 test chips show that an inaccuracy of ±0.2 °C (3σ) is achieved from 25 °C to 45 °C after one-point calibration. The average power consumption is 1.1 μW at a conversion speed of 2 Sa/s.

关键词： Temperature sensors Temperature measurement Capacitors Temperature dependence CMOS integrated circuits Low-power electronics

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Sub-threshold vlsi logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques

Sub-threshold VLSI logic family exploiting unbalanced pull-u...

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Asia and South Pacific Design Automation Conference

作者： Ming-Zhong Li Chio-In Ieong Man-Kay Law Pui-In Mak Mang-I Vai Sio-Hang Pun Rui P. Martins State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE University of Macau Macao China University of Macau Taipa Macau MO Instituto Superior Técnico Universidade de Lisboa Portugal

This paper presents a complete energy optimized sub-threshold standard cell library exploiting unbalanced pull-up/down (PU/PD) network, logical effort and inverse-narrow-width (INW) techniques. Individual logic cell is optimized for ultra-low-energy applications with low-to-moderate speed requirement. Three 14-tap 8-bit FIR filters are fabricated using a 0.18-μm CMOS technology, while one of them achieved the minimum energy/tap (0.0234 pJ) and 0.365 Figure-of-Merit (FoM) at 100 kHz, 0.31 V.

关键词： Finite impulse response filters MOS devices Transistors Logic gates Very large scale integration Energy efficiency Inverters

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A μNMR CMOS transceiver using a butterfly-coil input for integration with a digital microfluidic device inside a portable magnet

A μNMR CMOS transceiver using a butterfly-coil input for in...

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IEEE Asian Conference on Solid-state Circuits (ASSCC)

作者： Ka-Meng Lei Pui-In Mak Man-Kay Law Rui P. Martins The State Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE Universidade de Lisboa Macao Portugal

This paper reports a CMOS transceiver apt for integration with a digital microfluidic device, allowing electronic-automated sample management and measurement of micro-nuclear magnetic resonance (μNMR) signals inside a portable magnet. The transmitter (TX) employs an all-digital state control and a pulse sequence synthesizer to emit the exciting pulses for the samples. The receiver (RX) is led by a low-noise amplifier (LNA) using multi-stage NMOS-PMOS-complementary differential pairs, to achieve a sub-nV/√Hz input-referred noise. The RX baseband is a 6th-order Butterworth, dynamic-baseband-bandwidth lowpass filter (2.5 to 20 kHz), which suppresses the out-of-band noise and offers a fast recovery time between the exciting pulses, reducing the dead time of the RX for better sensitivity. Fabricated in 0.18-μm CMOS, the transceiver occupies a die area of 2.1 mm 2 and consumes 6.6/23.7 mW of power in the TX/RX mode.

关键词： Nuclear magnetic resonance Receivers Transceivers Decision support systems Solid state circuits CMOS integrated circuits Transmitters

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Preface

Analog Circuits and Signal Processing

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analog Circuits and signal Processing 2016年 vii页

作者： Lin, Zhicheng Mak, Pui-In Martins, Rui Paulo State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE University of Macau China Instituto Superior Técnico Universidade de Lisboa Lisbon Portugal

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A 0.3-V, 37.5-nW 1.5∼6.5-pF-input-range supply voltage tolerant capacitive sensor readout

A 0.3-V, 37.5-nW 1.5∼6.5-pF-input-range supply voltage tole...

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International Symposium on Integrated Circuits (ISIC)

作者： Su-Yan Fan Man-Kay Law Pui-In Mak Rui P. Martins The State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE University of Macau Macao China

A fully-digital capacitive sensor readout circuit based on capacitance controlled oscillators is presented. A two-step quantization scheme using SAR for coarse conversion and ΔΣ for fine conversion is introduced to extend the sensor input range while preserving the sensing accuracy. Systematic error analysis and optimization for the finite switch on-resistance and buffer input dependent delay are also outlined. Power supply insensitivity is ensured by the use of a pseudo-differential architecture and a ratiometric readout scheme. The complete sensor readout is implemented in a standard 0.18μm CMOS process. Simulation results show that the sensor readout circuit can achieve a wide input range from 1.5 to 6.5pF and a worst case power supply rejection ratio of 0.65% from 0.3V to 0.6V. For the ΔΣ conversion, a resolution of 7.4b at a conversion frequency of 318 Hz with an input capacitance of 4pF and a 0.3V supply is achieved. An average power is 37.5nW at 0.3V with a 4pF input capacitance, corresponding to a Figure-of-Merit (FoM) of 350fJ/conv-step.

关键词： Capacitive sensors Capacitance Switches Delays Simulation Capacitors

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