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A High-Current Scalable Parallel LDO Scheme With analog-Digital Merged Control for Small Current-Sharing Mismatch

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第10期70卷 3857-3866页

作者： Mao, Xiangyu Lu, Yan Wang, Chuang Martins, Rui P. Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau FST DECE Macau Peoples R China Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

Parallel connected low-dropout regulators (LDOs) are commonly used to share the large load current in communication baseband systems. This paper presents a PCB-friendly, reconfigurable master-slave parallel LDO scheme with analog regulation and digital distribution, to deliver Ampere-level load current with small current mismatches. The proposed LDO adopts a series analog-digital merged control, where the first loop is a high-gain analog error amplifier for high-accuracy regulation, and the second loop utilizes a 6-bit successive approximation register (SAR) analog-to-digital converter (ADC) for the tradeoffs between resolution, energy-efficiency, and fast response. Each LDO can be configured into the master or slave mode. When multiple LDOs are connected in parallel, the master LDO also controls the digital power cells in the slave LDOs. By employing an auxiliary constant current control, the power cells in each LDOs work as a constant current source array. The same control code naturally enables the output current balancing among each LDOs. Fabricated in 65-nm CMOS, the proposed LDO obtains an excellent load regulation of < 1.5mV/A across the full load range of 0-1A, with 99.9% peak current efficiency. For four parallel LDOs with each delivering 1-A load current, the measured current-sharing mismatch is only < 0.76% with no additional external components.

关键词： Low-dropout regulator (LDO) hybrid control master-slave parallel current-sharing dual-loop control

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A 24-V-Input Highly Integrated Interleaved-Inductor Multiple Step-Down Hybrid DC-DC Converter With Inherent Current Equalization Characteristics

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IEEE JOURNAL OF SOLID-state CIRCUITS 2024年第9期59卷 2895-2906页

作者： Zhang, Xiongjie Zhao, Anyang Ma, Qiaobo Jiang, Yang Law, Man-Kay Martins, Rui P. Mak, Pui-In Univ Macau Inst Microelect IME State Key Lab Analog & Mixed Signal VLSI Fac Sci & Technol FST Taipa Macau Peoples R China Univ Macau Fac Sci & Technol FST Dept ECE Taipa Macau Peoples R China

This article presents a highly integrated hybrid dc-dc converter with a 24-V input, employing the interleaved-inductor multiple step-down (IL-MSD) topology. The proposed design ensures symmetric power-stage operations, addressing inductor current ( I-L) imbalance without complex regulation control. It also optimizes current distribution among internal conduction branches, reducing conduction losses and input capacitor requirements. In addition, we propose an on-chip gate-driving scheme utilizing a high-voltage (HV) floating current (HVFC) source and HV charge storage technique, eliminating external bootstrap capacitors and extra HV supplies. Fabricated in a 180-nm BCD process, the converter chip integrates all-N-type power switches, gate drivers (GDs), startup/pre-charge circuits, and control blocks within a 4.7-mm $<^>{2}$ footprint. Using two 1- $\mu$ H compact inductors and four 1- $\mu$ F flying capacitors, the converter regulated a 1-3.5-V output from a 24-V input with a peak efficiency of 90.4% under a 1.2-A load. The maximum load current reaches 5 A with an 82% efficiency. The achieved on-chip and overall power densities are 3.51 and 0.62 W/mm(3) , respectively.

关键词： Switches Topology Inductors Video recording Power system measurements Density measurement Capacitors DC-DC converter fully symmetric high step-down hybrid topology interleaved inductor on-chip gate driver (GD)

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A Fully Synthesizable All-Digital Dual-Loop Distributed Low-Dropout Regulator

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IEEE JOURNAL OF SOLID-state CIRCUITS 2024年第6期59卷 1871-1882页

作者： Mao, Xiangyu Lu, Yan Martins, Rui P. Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau FST DECE Macau Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

Distributed low-dropout voltage regulators (LDOs) can mitigate the global IR drop and improve the local transient performances for a high-current large-area power delivery network. However, they also face integration and current-sharing challenges. To tackle these challenges, this article presents an all-digital dual-loop distributed LDO with one global controller (GC) and multiple scalable local voltage regulators (LVRs). For fully synthesizable and easy integration, all the control circuits are implemented using standard digital cells. In each LVR, we use a 5-bit time-to-digital converter (TDC) for fast local voltage sensing. The global integral loop provides the dynamic reference bits for all the LVRs, compensating the TDC PVT variations in the LVRs. This all-digital comparator-TDC quantizer, combined with coarse-fine tuning and asynchronous window control, enables the proposed LDO architecture to obtain high output accuracy and one-cycle transient response. For current balancing in distributed scenarios, we introduce a digital primary-secondary one-time calibration scheme to tackle the mismatches among the local TDCs. A distributed LDO prototype with one GC and nine LVRs is implemented in a 28-nm bulk CMOS process. Measurements with one LVR and multiple LVRs demonstrate the stability and scalability of the proposed architecture. With nine LVRs, the measured droop is 54 mV under a 1.35-A/10-ns sharp load step. We also obtain a good load regulation of 3 mV/A, a peak current efficiency of 99.67%, and a current density of 16.7 A/mm(2) .

关键词： Regulators Voltage control Regulation Circuit stability Calibration Transient response Transient analysis Asynchronous window control distributed LDO dual loop fully synthesizable low-dropout regulator primary-secondary calibration

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A 0.004-mm² 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS

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IEEE JOURNAL OF SOLID-state CIRCUITS 2023年第11期58卷 3179-3193页

作者： Zhang, Chenghao Wei, Jiangbo Chen, Yong Liu, Maliang Yang, Yintang Xidian Univ Sch Microelect Xian Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI IME & ECE FST Taipa Macao Peoples R China

This article reports an area-power-efficient 7-bit 2-GS/s time-domain analog-to-digital converter (TD-ADC) based on a gated ring oscillator (GRO). A pulse generator (PG) with the dead-zone elimination technique is devised for maximizing the linearity of the gated signal. The GRO-based time-todigital converter employs a robust interpolation that effectively increases the interpolation accuracy of the GRO and improves the overall resolution. Also, a phase-tracking sampling generator is developed to suppress the leakage effect of the GRO and enhance the energy efficiency of the time-to-digital conversion. Moreover, a digital-assisted calibration technique is designed to eliminate the quantization error caused by the time-folding offset. The TD-ADC prototype is fabricated in a 28-nm CMOS process with an active area of 0.004 mm(2). It scores a measured peak SNDR of 38.63 dB and an SFDR of 50.66 dB at the conversion rate of 2 GS/s, along with the figure of merit (FoM) of 31.4 fJ/conversion step.

关键词： analog-to-digital converter (ADC) calibration CMOS folding gated ring oscillator (GRO) interpolation pulse generator (PG) time domain (TD) voltage domain (VD)

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A Hybrid Single-Inductor Bipolar Triple-Output DC-DC Converter With High-Quality Positive Outputs for AMOLED Displays

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第1期70卷 506-517页

作者： Mao, Fangyu Lu, Yan Maloberti, Franco Martins, Rui P. Univ Macau DECE FST Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Pavia Dept Elect Comp & Biomed Engn I-27100 Pavia Italy

This paper presents a hybrid single-inductor bipolar triple-output (SIBTO) DC-DC converter for active-matrix organic light-emitting diode (AMOLED) displays. Generating the bipolar rails V-OP and V-ON for the pixel array and the analog rail AV (DD) for the source driver with a single inductor greatly reduces the system size and cost. This work adopts the floating negative output topology for an ultra-clean positive output. In addition, we propose a push-pull charge balancer to compensate and regulate the V-OP , improving the line and load regulation with continuous currents and acceptable power consumption. This work also proposed a slow-comparator based ordered power distributive control (SC-OPDC) to regulate the AV (DD) with a pulse-skipping scheme to reduce the power loss. The designed power transistor buffers with adaptive deadtime control improve power conversion efficiency and decrease the required minimum load current of AV $_{\mathrm{DD}}$ . The proposed SIBTO converter, implemented in 0.18- mu m BCD process, operates at 1.67 MHz. It achieves a peak efficiency of 94.1% at 0.88 W output and a maximum output power of 3.67 W with an efficiency of 87%. The maximum output voltage ripples are 5 mV, 17 mV, and 7.5 mV for V-OP , V-ON , and AV (DD), respectively.

关键词： Active matrix organic light emitting diodes Regulation Inductors Topology Switches Rails Capacitors AMOLED display hybrid converter bipolar triple output DC-DC converter floating negative output ordered power distributive control pulse skipping adaptive deadtime control single-inductor multiple output (SIMO)

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Comprehensive analysis of MOSFET threshold voltage extraction method considering DIBL effect from 300 K down to 10 K

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SOLID-state ELECTRONICS 2025年 224卷

作者： Ma, Zhizhao Su, Hao Lin, Yuhuan Zhou, Shenghua Zhou, Feichi Liu, Xiaoguang Lin, Longyang Li, Yida Chen, Kai Southern Univ Sci & Technol SUSTech Shenzhen 518055 Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI IME ECE FST Macau Peoples R China Int Quantum Acad Shenzhen 518048 Peoples R China

It is well known that different threshold voltage (Vth) extraction methods exhibit inconsistencies with respect to different drain voltage (Vd). This inconsistency becomes disruptive when temperature is considered for cryogenic applications such as quantum computing. This investigation examines various V th extraction methods from room down to cryogenic temperatures, with a particular emphasis on how different Vd values combined with extraction methods behave as temperature decreases. For the first time, we find that the square root Id method maintains consistency regardless of V d , from 300 K all the way down to 10 K is identified. This provides a good insight into how the Drain-Induced Barrier Lowering (DIBL) effect changes with temperature, and positions the square root Id method as a reliable tool for V th extraction in cryogenic temperature.

关键词： Threshold Voltage Extraction Method Cryogenic DIBL

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A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors

A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32...

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2023 IEEE Symposium on vlsi Technology and Circuits, vlsi Technology and Circuits 2023

作者： Zhang, Minglei Cao, Yuefeng Zhu, Yan Chan, Chi-Hang Martins, R.P. University of Macau State-Key Laboratory of Analog and Mixed-Signal Vlsi Ime Macao China

ISBN: (纸本)9784863488069

This paper presents a 32× low-noise dynamic amplifier (DA) with a linearity-shifting technique, facilitating a 15b pipelined-SAR ADC with 80 dB SNR@DC. The linearity-shifted DA decouples the fundamental conflict between the noise and linearity in conventional DAs, rending a THD below -60dB at 0.8Vpp,diff output swing. Moreover, the reference voltages are stabilized by the cost-effective mounted-over-die bypass capacitors. The 60MS/s ADC achieves 95.8dB and 87.3dB SFDR with a DC and Nyquist input, respectively, and an input noise density of 10.2nV/√Hz. © 2023 JSAP.

关键词： Cost effectiveness

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A Three-Fine-Level Buck-Boost Hybrid Converter Achieving Half- VIN -Stress on All Switches and Fast Transient Response

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IEEE JOURNAL OF SOLID-state CIRCUITS 2025年第5期60卷 1719-1730页

作者： Zhao, Shuangxing Zhan, Chenchang Zhang, Zhaobo Bai, Xianglong Huang, Chenyu Lu, Yan Southern Univ Sci & Technol Sch Microelect Shenzhen 518055 Peoples R China Univ Macau FST DECE Inst Microelect State Key Lab Analog Mixed Signal VLSI Taipa 999078 Macau Peoples R China Univ Macau Inst Microelect FST DECE Taipa 999078 Macau Peoples R China Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China

This article presents a non-inverting three-fine-level buck-boost (3FLBB) hybrid converter suitable for lithium-ion (Li-ion) batteries. With seven power switches and two flying capacitors, the proposed 3FLBB converter produces the voltage of switching node between V-IN/2, V-IN , and 3 V-IN /2, which supports buck, boost, and buck-boost modes, and with smooth mode changes. Here, one of the two flying capacitors is used to drive the inductor (L), while another one is used to ensure that V-DS of each power switch is within 1/2V(IN) in all phases. Hence, the voltage stress of all the power switches is reduced to half-V-IN, and the normalized equivalent resistance and switching losses are greatly reduced by using two 1.8-V switches instead of two 5-V switches. Since the three modes all have buck-like operation, the average inductor current is reduced to always equal to the output current. Meanwhile, they all have continuous output current, similar complex pole pairs, and no right half-plane (RHP) zero, which enables fast load transient response. This design is implemented by only 1.8-V devices of a standard 0.18-mu m CMOS process, covering an input voltage range from 2.8 to 4.2 V. A 98.2% peak efficiency is measured at 2-MHz switching frequency with 2.2-mu H L, two 10-mu F mu F flying capacitors, and one 10-mu F output capacitor. It can deliver an output current of 50-1000 mA at a 3.3-V regulated output voltage. Moreover, the measured results show that this design achieves a significant improvement on undershoot and overshoot voltage than the previous works.

关键词： Voltage Inductors Capacitors Topology MOSFET Voltage measurement Transient response Buck-boost dc-dc converter fast transient response flying capacitor hybrid converter lithium-ion (Li-ion) battery no right-half-plane zero switched capacitor three-fine-level buck-boost (3FLBB)

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All Rivers Flow to the Sea: A High-Density Wireless Power Receiver With Split-Dual-Path and Hybrid-Quad-Path Step-Down Rectifying Conversion

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IEEE JOURNAL OF SOLID-state CIRCUITS 2023年第11期58卷 3127-3137页

作者： Lin, Zixiao Lu, Yan Mao, Fangyu Wang, Chuang Martins, Rui P. Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Dept Elect & Comp Engn DECE Fac Sci & Technol FST Macau Peoples R China

This article presented a wireless power receiver (RX) with a split-dual-path and merged switched-capacitor-inductor hybrid-quad-path (S2H4) step-down rectifying conversion for high output current. It can obtain the V-ac amplitude as high as 3V(OUT), which increases the output power of the resonant tank. With multiple paths conducting currents to the load, the current stress on the power inductor has been significantly reduced, resulting in lower inductor power loss. The S2H4 wireless power RX is also compatible with a cable charging function, with the conversion part hardware being reused. Fabricated in a 0.18-mu m high-voltage (HV) SOI process, this proposed RX obtains 8.8-W maximum output power, and peak efficiencies of 85.2% and 91% for wireless and cable charging, respectively.

关键词： Inductors Wireless communication Rectifiers Topology Capacitors Receivers Power generation

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A Switchless Dual-core Triple-Mode VCO Achieving 7.1-to-15.7 GHz Frequency Tuning Range and 202.1 dBc/Hz Peak FoM at 3.7 Kelvin

A Switchless Dual-core Triple-Mode VCO Achieving 7.1-to-15.7...

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IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

作者： Wu, Yue Peng, Yatao Huo, Benhao Yin, Jun Martins, Rui P. Mak, Pui In Univ Macau State Key Lab Analog & Mixed Signal VLSI IME ECE FST Taipa Macao Peoples R China Univ Lisbon Inst Super Tecn Lisbon Portugal

ISBN: (纸本)9798350359480;9798350359473

We reported a dual-core triple-mode voltage-controlled oscillator (VCO) to adapt to the low power consumption and large frequency tuning range (FTR) of the signal source in quantum interface systems. We proposed using only magnetic and inductive tuning elements for resonance splitting to construct the VCO's triple-mode LC tank. This avoids the FTR sacrifice when using a conventional capacitive tuning element to build the multi-mode tank. To reduce the power consumption of the negative transconductance (-G(M)) cells in the multicore multi-mode VCO, we proposed a structure that provides a triple oscillating mode with only two -G(M) cores. In addition, to overcome the deterioration of phase noise (PN) due to the switch-on resistances, we introduced a switching -G(M) technique for mode selection without using the MOSFET switches. The wideband VCO was specifically designed for cryogenic operation, utilizing a 28 nm CMOS technology. The measured results demonstrate an FTR of 7.1-15.7 GHz (75.4%) and a peak figure-of-merit (FoM) of 202.1 dBc/Hz at 3.7 Kelvin.

关键词： VCO mode-switching switch-less cryogenic CMOS quantum interface frequency tuning range

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