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检索条件"机构=State-Key Laboratory of Analog and Mixed-Signal VLSI/IME-DECE/FST"

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Design considerations of a low-noise receiver front-end and its spiral coil for portable NMR screening

Design considerations of a low-noise receiver front-end and ...

引用

IEEE Asia-Pacific Conference on Circuits and Systems

作者： Diyang Zhao Ka-Meng Lei Pui-In Mak Man-Kay Law Rui P. Martins The State Key Laboratory of Analog and Mixed-Signal VLSI and FST ECE Universidade de Lisboa Portugal China

This paper reports the co-design of a low-noise receiver front-end and its exciting-sensing coil for portable nuclear magnetic resonance (NMR) screening of chemical/biological droplets operating at 21.3MHz (0.5T magnet). To minimize the noise contribution of the receiver front-end and its coil compared to the induced signal, EM analysis is involved to optimize the geometry of the off-chip coil with the input-referred noise of the receiver front-end taken into account. By choosing a proper geometry of the coil, the resulted SNR of the receiver front-end was shown to be maximized with the dedicated input-referred noise of the receiver. Simulated in 180nm CMOS, the receiver front-end shows an input-referred noise as low as 920.11pV/√Hz at 25.2mW of power, and the estimated die area is ~2mm 2 .

关键词： Coils Receivers Nuclear magnetic resonance signal to noise ratio Mixers Geometry

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A 26.3 dBm 2.5 to 6 GHz wideband class-D switched-capacitor power amplifier with 40% peak PAE

A 26.3 dBm 2.5 to 6 GHz wideband class-D switched-capacitor ...

引用

IEEE Conference on Electron Devices and Solid-state Circuits

作者： Xing-Qiang Peng Wei-Han Yu Pui-In Mak Rui P. Martins The State Key Laboratory of Analog and Mixed-Signal VLSI and FST ECE University of Macau Macao China On leave from Instituto Superior Instituto Superior Técnico Universidade de Lisboa Portugal

This paper describes a wideband class-D RF power amplifier (PA) featuring switched-capacitor (SC) modulation, a high-order LC-matching network (MN) and a reliability-aware supply-voltage boosting technique. Simulated in 65-nm CMOS at an elevated 3.2-V supply, the rms voltage stressed on each device is managed to be well within the reliability limits. The broadband coverage is from 2.5 to 6 GHz with peak power-added efficiency (PAE) of 40% at 26.4 dBm output power. After digital predistortion, the EVM is controlled

关键词： Power amplifiers Wideband Power generation Switches Manganese Reliability Modulation

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A 2.93μW 8-bit capacitance-to-RF converter for movable laboratory mice blood pressure monitoring

A 2.93μW 8-bit capacitance-to-RF converter for movable labo...

引用

5th Asia Symposium on Quality Electronic Design, ASQED 2013

作者： Lei, Ka-Meng Mak, Pui-In Law, Man-Kay Martins, R.P. State-Key Laboratory of Analog and Mixed Signal VLSI and FST/ECE University of Macau China

ISBN: (纸本)9781479913145

An ultra-low-power capacitance-to-RF (C/RF) converter for laboratory mice blood pressure monitoring is proposed. Unlike the conventional design involving capacitance-to-analog (C/A) conversion followed by analog-to-digital (A/D) conversion, the proposed front-end is a direct capacitance-to-digital (C/D) converter that can simplify the hardware while saving both power and area. The C/D converter also features an automatic capacitance-range finder mapping the input capacitance range to the full scale of the digitization core. The generated digital data is compressed before driving the back-end RF transmitter, which is based on a power-ON/OFF VCO with direct FSK modulation operated at the 915-MHz ISM band. Optimized in 65-nm CMOS, the simulated 8-bit 6.4-kSa/s C/RF converter exhibits a 7.5 effective number of bit (ENOB) and a ∼0.7 V pp output swing at the RF transmitter output, while drawing 2.93 μW of power. The DNL and INL are ±0.125 and ±0.188 LSB, respectively. The attained capacitance sensing resolution is equivalent to 1.25 fF/LSB. © 2013 IEEE.

关键词： Capacitance

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A wideband multi-stage inverter-based driver amplifier for IEEE 802.22 WRAN transmitters

A wideband multi-stage inverter-based driver amplifier for I...

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5th Asia Symposium on Quality Electronic Design, ASQED 2013

作者： Qi, Geng-Zhen Un, Ka-Fai Yu, Wei-Han Mak, Pui-In Martins, Rui P. State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE University of Macau China TU of Lisbon Portugal

ISBN: (纸本)9781479913145

This paper proposes a wideband multi-stage inverter-based driver amplifier (DA) suitable for IEEE 802.22 wireless regional area network (WRAN) transmitters. In order to optimize the voltage gain, power, linearity and load drivability, the DA employs two cascaded inverters followed by a source follower, in which the second inverter employs resistive feedback and an inverter-based active load to achieve linearization. Simulated in 65 nm CMOS, the achieved voltage gain is 17.6 dB and the power is 14.6 mW at 1.2 V. The -3 dB bandwidth is 5.6 MHz to 2.17 GHz. For a 3rd-order intermodulation distortion (IMD3) of -45 dBc, the output power reaches -7.3 dBm. © 2013 IEEE.

关键词： Electric inverters

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Systematic analysis and cancellation of kickback noise in a dynamic latched comparator

Systematic analysis and cancellation of kickback noise in a ...

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作者： Lei, Ka-Meng Mak, Pui-In Martins, Rui P. State-Key Laboratory of Analog and Mixed-Signal VLSI FST-ECE University of Macau China Instituto Superior Técnico U of Lisbon Lisbon Portugal

A dynamic latched comparator can suffer from three non-idealities: offset voltage, random noise and kickback noise. Specifically in an analog-to-digital converter (ADC) the kickback noise of a comparator can noticeably affect the settling time and accuracy of the decision. This work offers an analytical treatment of kickback noise generation, and proposes a synchronized kickback noise cancellation technique, which is achieved via placing clocked NMOS-PMOS capacitors at the proper nodes to cancel out effectively those unwanted charges (electrons or holes) under different operating regions of the MOS devices. The technique is clock-rate insensitive and particularly suitable for the SAR-type ADC as it will not alter the charge stored in the capacitor array. Optimized in 65-nm CMOS the kickback noise is pp, the kickback noise of the proposed comparator comparing with the conventional one is improved by 48×, from 6.27 to 0.13 LSB. © 2013 Springer Science+Business Media New York.

关键词： Comparators (optical)

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Sub-threshold standard cell library design for ultra-low power biomedical applications

Sub-threshold standard cell library design for ultra-low pow...

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Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

作者： Ming-Zhong Li Chio-In Ieong Man-Kay Law Pui-In Mak Mang-I Vai Rui P. Martins Biomedical Engineering Laboratory FST and State-Key Laboratory of Analog and Mixed-Signal VLSI University of Macau Macao China State-Key Laboratory of Analog and Mixed-Signal VLSI University of Macau Macao China

ISBN: (纸本)9781457702150

Portable/Implantable biomedical applications usually exhibit stringent power budgets for prolonging battery life time, but loose operating frequency requirements due to small bio-signal bandwidths, typically below a few kHz. The use of sub-threshold digital circuits is ideal in such scenario to achieve optimized power/speed tradeoffs. This paper discusses the design of a sub-threshold standard cell library using a standard 0.18-μm CMOS technology. A complete library of 56 standard cells is designed and the methodology is ensured through schematic design, transistor width scaling and layout design, as well as timing, power and functionality characterization. Performance comparison between our sub-threshold standard cell library and a commercial standard cell library using a 5-stage ring oscillator and an ECG designated FIR filter is performed. Simulation results show that our library achieves a total power saving of 95.62% and a leakage power reduction of 97.54% when compared with the same design implemented by the commercial standard cell library (SCL).

关键词： Libraries Standards Transistors Layout Finite impulse response filters Power demand Threshold voltage

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Standard cell library design with voltage scaling and transistor sizing for ultra-low-power biomedical applications

Standard cell library design with voltage scaling and transi...

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IEEE Conference on Electron Devices and Solid-state Circuits

作者： Chio-In Ieong Mingzhong Li Man-Kay Law Pui-In Mak Mang-I Vai Peng-Un Mak Feng Wan Rui P. Martins State Key Laboratory of Analog and Mixed-Signal VLSI and FST ECE University of Macau Macao China

ISBN: (纸本)9781467325240

This paper reports the design and optimization of a standard cell library in 0.18μm CMOS, together with the analysis on voltage scaling and transistor sizing for ultra-low power biomedical applications. By simulating with a 8-bit 4-tap FIR filter at 0.6V clocked 100kHz, the design achieves 18.6× and 1.55× lower power consumption comparing to a commercial standard cell library working at nominal voltage 1.8V and re-characterized 0.6V.

关键词： Transistors Capacitance Libraries Logic gates Very large scale integration Power demand Inverters

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An ultra-low power CMOS smart temperature sensor for clinical temperature monitoring

An ultra-low power CMOS smart temperature sensor for clinica...

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IEEE Conference on Electron Devices and Solid-state Circuits

作者： Tao Wu Man-Kay Law Pui-In Mak Rui P. Martins State-Key Laboratory of Analog and Mixed Signal VLSI and FST ECE University of Macau Macao China

ISBN: (纸本)9781467325240

This paper presents an ultra-low power, high accuracy CMOS smart temperature sensor for clinical temperature monitoring applications. The proposed sensor trades off the sensing range and the conversion speed with improved accuracy and power consumption. The sensor consists of a power optimized analog frontend and a delta-sigma analog-to-digital converter (ΔΣADC) with dynamic element matching (DEM), as well as a modified gain stage to optimize the sensing range and relax the resolution requirement. Using a standard 0.18μm CMOS technology, the achieved accuracy and conversion speed after one-point calibration from 27°C to 47°C are ±0.1°C and 2 sample/s, respectively, while consuming only 1.1μW power.

关键词： Temperature sensors Temperature measurement CMOS integrated circuits Monitoring Accuracy Low-power electronics

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A 2.93μW 8-bit capacitance-to-RF converter for movable laboratory mice blood pressure monitoring

A 2.93μW 8-bit capacitance-to-RF converter for movable labo...

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Asia Symposium on Quality Electronic Design, ASQED

作者： Ka-Meng Lei Pui-In Mak Man-Kay Law R. P. Martins State-Key Laboratory of Analog and Mixed Signal VLSI and FST ECE University of Macau Macao China University of Macau Taipa Macau MO

An ultra-low-power capacitance-to-RF (C/RF) converter for laboratory mice blood pressure monitoring is proposed. Unlike the conventional design involving capacitance-to-analog (C/A) conversion followed by analog-to-digital (A/D) conversion, the proposed front-end is a direct capacitance-to-digital (C/D) converter that can simplify the hardware while saving both power and area. The C/D converter also features an automatic capacitance-range finder mapping the input capacitance range to the full scale of the digitization core. The generated digital data is compressed before driving the back-end RF transmitter, which is based on a power-ON/OFF VCO with direct FSK modulation operated at the 915-MHz ISM band. Optimized in 65-nm CMOS, the simulated 8-bit 6.4-kSa/s C/RF converter exhibits a 7.5 effective number of bit (ENOB) and a ~0.7 V pp output swing at the RF transmitter output, while drawing 2.93 μW of power. The DNL and INL are ±0.125 and ±0.188 LSB, respectively. The attained capacitance sensing resolution is equivalent to 1.25 fF/LSB.

关键词： Capacitance Capacitors Blood pressure Frequency shift keying Biomedical monitoring Radio frequency Arrays

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A wideband multi-stage inverter-based driver amplifier for IEEE 802.22 WRAN transmitters

A wideband multi-stage inverter-based driver amplifier for I...

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Asia Symposium on Quality Electronic Design, ASQED

作者： Geng-Zhen Qi Ka-Fai Un Wei-Han Yu Pui-In Mak Rui P. Martins State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE University of Macau Macao China University of Macau Taipa Macau MO

This paper proposes a wideband multi-stage inverter-based driver amplifier (DA) suitable for IEEE 802.22 wireless regional area network (WRAN) transmitters. In order to optimize the voltage gain, power, linearity and load drivability, the DA employs two cascaded inverters followed by a source follower, in which the second inverter employs resistive feedback and an inverter-based active load to achieve linearization. Simulated in 65 nm CMOS, the achieved voltage gain is 17.6 dB and the power is 14.6 mW at 1.2 V. The -3 dB bandwidth is 5.6 MHz to 2.17 GHz. For a 3 rd -order intermodulation distortion (IMD3) of -45 dBc, the output power reaches -7.3 dBm.

关键词： Linearity Inverters Gain Wideband Power generation Power amplifiers Radio transmitters

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