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共 216 条记录，以下是201-210 订阅

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An ultra-low power CMOS smart temperature sensor for clinical temperature monitoring

An ultra-low power CMOS smart temperature sensor for clinica...

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IEEE Conference on Electron Devices and Solid-state Circuits

作者： Tao Wu Man-Kay Law Pui-In Mak Rui P. Martins State-Key Laboratory of Analog and Mixed Signal VLSI and FST ECE University of Macau Macao China

ISBN: (纸本)9781467325240

This paper presents an ultra-low power, high accuracy CMOS smart temperature sensor for clinical temperature monitoring applications. The proposed sensor trades off the sensing range and the conversion speed with improved accuracy and power consumption. The sensor consists of a power optimized analog frontend and a delta-sigma analog-to-digital converter (ΔΣADC) with dynamic element matching (DEM), as well as a modified gain stage to optimize the sensing range and relax the resolution requirement. Using a standard 0.18μm CMOS technology, the achieved accuracy and conversion speed after one-point calibration from 27°C to 47°C are ±0.1°C and 2 sample/s, respectively, while consuming only 1.1μW power.

关键词： Temperature sensors Temperature measurement CMOS integrated circuits Monitoring Accuracy Low-power electronics

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A 2.93μW 8-bit capacitance-to-RF converter for movable laboratory mice blood pressure monitoring

A 2.93μW 8-bit capacitance-to-RF converter for movable labo...

引用

Asia Symposium on Quality Electronic Design, ASQED

作者： Ka-Meng Lei Pui-In Mak Man-Kay Law R. P. Martins State-Key Laboratory of Analog and Mixed Signal VLSI and FST ECE University of Macau Macao China University of Macau Taipa Macau MO

An ultra-low-power capacitance-to-RF (C/RF) converter for laboratory mice blood pressure monitoring is proposed. Unlike the conventional design involving capacitance-to-analog (C/A) conversion followed by analog-to-digital (A/D) conversion, the proposed front-end is a direct capacitance-to-digital (C/D) converter that can simplify the hardware while saving both power and area. The C/D converter also features an automatic capacitance-range finder mapping the input capacitance range to the full scale of the digitization core. The generated digital data is compressed before driving the back-end RF transmitter, which is based on a power-ON/OFF VCO with direct FSK modulation operated at the 915-MHz ISM band. Optimized in 65-nm CMOS, the simulated 8-bit 6.4-kSa/s C/RF converter exhibits a 7.5 effective number of bit (ENOB) and a ~0.7 V pp output swing at the RF transmitter output, while drawing 2.93 μW of power. The DNL and INL are ±0.125 and ±0.188 LSB, respectively. The attained capacitance sensing resolution is equivalent to 1.25 fF/LSB.

关键词： Capacitance Capacitors Blood pressure Frequency shift keying Biomedical monitoring Radio frequency Arrays

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A wideband multi-stage inverter-based driver amplifier for IEEE 802.22 WRAN transmitters

A wideband multi-stage inverter-based driver amplifier for I...

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Asia Symposium on Quality Electronic Design, ASQED

作者： Geng-Zhen Qi Ka-Fai Un Wei-Han Yu Pui-In Mak Rui P. Martins State-Key Laboratory of Analog and Mixed-Signal VLSI and FST-ECE University of Macau Macao China University of Macau Taipa Macau MO

This paper proposes a wideband multi-stage inverter-based driver amplifier (DA) suitable for IEEE 802.22 wireless regional area network (WRAN) transmitters. In order to optimize the voltage gain, power, linearity and load drivability, the DA employs two cascaded inverters followed by a source follower, in which the second inverter employs resistive feedback and an inverter-based active load to achieve linearization. Simulated in 65 nm CMOS, the achieved voltage gain is 17.6 dB and the power is 14.6 mW at 1.2 V. The -3 dB bandwidth is 5.6 MHz to 2.17 GHz. For a 3 rd -order intermodulation distortion (IMD3) of -45 dBc, the output power reaches -7.3 dBm.

关键词： Linearity Inverters Gain Wideband Power generation Power amplifiers Radio transmitters

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A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure

A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact ...

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2012 Symposium on vlsi Circuits, vlsiC 2012

作者： Chan, Chi-Hang Zhu, Yan Sin, Sai-Weng U, Seng-Pan Martins, R.P. State-Key Laboratory of Analog and Mixed Signal VLSI FST University of Macau China Limited China Instituto Superior Técnico/TU of Lisbon Portugal

ISBN: (纸本)9781467308458

An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. To enhance speed and save power, the prototype utilizes segmentation switching and custom-designed DAC array with high density in a low parasitic layout structure. It operates at 1GS/s from 1V supply without interleaving calibration and consumes 3.8mW of power, exhibiting a FoM of 24fJ/conversion step. The ADC occupies an active area of 0.013mm2 in 65nm CMOS including on-chip offset calibration. © 2012 IEEE.

关键词： analog to digital conversion

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A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC

A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC

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2012 Symposium on vlsi Circuits, vlsiC 2012

作者： Zhu, Yan Chan, Chi-Hang Sin, Sai-Weng U, Seng-Pan Martins, R.P. State-Key Laboratory of Analog and Mixed Signal VLSI FST University of Macau China Limited China Instituto Superior Técnico/TU of Lisbon Portugal

ISBN: (纸本)9781467308458

A 10b 500MS/s ADC is presented that shares a full-speed SAR at front-end and interleaves the pipelined residue amplification with shared opamp and 2 nd-stage SAR ADCs, which achieves high speed, low power and compact area. The prototype ADC in 65nm CMOS achieves a mean SNDR of 55.4dB with 8.2mW power dissipation at 1.2V. The active die area including the offset calibrations is 0.046mm2. © 2012 IEEE.

关键词： Operational amplifiers

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A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique

A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with...

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38th European Solid state Circuits Conference, ESSCIRC 2012

作者： Wang, Rui Chio, U-Fat Sin, Sai-Weng Seng-Pan, U. Wang, Zhihua Martins, Rui Paulo Institute of Microelectronic Tsinghua University Beijing China State-Key Laboratory of Analog and Mixed Signal VLSI FST University of Macao China Limited China Instituto Superior Técnico TU of Lisbon Portugal

ISBN: (纸本)9781467322126

This paper presents a 12-bit 110MS/s 4-stage pipelined SAR ADC integrated through a single low-gain op-amp. A ratio-based GEC (Gain Error Calibration) technique based on op-amp sharing is proposed to reduce the complexity of digital calibration circuit. Only one PN (Pseudo-random Number) signal is employed to perform the dither injection but calibrate multiple gain errors, and thus accelerates the convergence speed, gets rid of input signal reduction and minimizes the analog modification due to the background calibration. The effectiveness of the architecture is verified in 65-nm CMOS chips whose analog core area is 0.12 mm2 only. The ADC obtains an average SNDR of 63 dB and SFDR of 75.2 dB at 110MS/s consuming analog power of 11.5mW from a 1.2-V supply. Only 40 thousand points are needed to achieve desirable SNDR with the proposed calibration technique. © 2012 IEEE.

关键词： Operational amplifiers

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A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC

A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC

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Symposium on vlsi Circuits

作者： Yan Zhu Chi-Hang Chan Sai-Weng Sin Seng-Pan U R.P. Martins State-Key Laboratory of Analog and Mixed Signal VLSI FST University of Macau Macau China

A 10b 500MS/s ADC is presented that shares a full-speed SAR at front-end and interleaves the pipelined residue amplification with shared opamp and 2 nd -stage SAR ADCs, which achieves high speed, low power and compact area. The prototype ADC in 65nm CMOS achieves a mean SNDR of 55.4dB with 8.2mW power dissipation at 1.2V. The active die area including the offset calibrations is 0.046mm 2 .

关键词： Calibration Switches Semiconductor device measurement CMOS integrated circuits Capacitance Very large scale integration Error correction

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A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure

A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact ...

引用

Symposium on vlsi Circuits

作者： Chi-Hang Chan Yan Zhu Sai-Weng Sin Seng-Pan U R.P. Martins State-Key Laboratory of Analog and Mixed Signal VLSI FST University of Macau Macao China Instituto Superior Técnico Technical University of Lisbon Portugal

An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. To enhance speed and save power, the prototype utilizes segmentation switching and custom-designed DAC array with high density in a low parasitic layout structure. It operates at 1GS/s from 1V supply without interleaving calibration and consumes 3.8mW of power, exhibiting a FoM of 24fJ/conversion step. The ADC occupies an active area of 0.013mm 2 in 65nm CMOS including on-chip offset calibration.

关键词： Arrays Switches Capacitors Layout Calibration Metals Very large scale integration

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A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique

A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with...

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European Conference on Solid-state Circuits (ESSCIRC)

作者： Rui Wang U-Fat Chio Sai-Weng Sin U. Seng-Pan Zhihua Wang Rui Paulo Martins Institute of Microelectronic Tsinghua University Beijing China State-Key Laboratory of Analog and Mixed Signal VLSI FST University of Macao Macao China Instituto Superior Técnico/TUL Portugal

This paper presents a 12-bit 110MS/s 4-stage pipelined SAR ADC integrated through a single low-gain op-amp. A ratio-based GEC (Gain Error Calibration) technique based on op-amp sharing is proposed to reduce the complexity of digital calibration circuit. Only one PN (Pseudo-random Number) signal is employed to perform the dither injection but calibrate multiple gain errors, and thus accelerates the convergence speed, gets rid of input signal reduction and minimizes the analog modification due to the background calibration. The effectiveness of the architecture is verified in 65-nm CMOS chips whose analog core area is 0.12 mm 2 only. The ADC obtains an average SNDR of 63 dB and SFDR of 75.2 dB at 110MS/s consuming analog power of 11.5mW from a 1.2-V supply. Only 40 thousand points are needed to achieve desirable SNDR with the proposed calibration technique.

关键词： Calibration Capacitors Semiconductor device measurement Convergence CMOS integrated circuits Gain Pipelines

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A real-time heart beat detector and quantitative investigation based on FPGA

A real-time heart beat detector and quantitative investigati...

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3rd IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2011

作者： Dong, Cheng Ieong, Chio In Vai, Mang I. Mak, Peng Un Mak, Pui In Wan, Feng Biomedical Engineering Laboratory FST and State-Key Laboratory of Analog and Mixed-Signal VLSI University of Macau China

ISBN: (纸本)9781457716096

A Field Programmable Gate Array (FPGA) based system for single-lead electrocardiogram signal QRS complex detection is presented in this paper. The system consists of Quadratic Spline wavelet transform, moving average filter, signed squaring and a Modulus Maxima Pair Recognition module. The parallel and pipelined architecture of the system allows a maximum throughput equals 46MS/s. The QRS Complex detection accuracy is validated using MIT/BIH arrhythmia database, in which, sensitivity of 99.35% and predictivity of 99.70% are achieved. Less than 2000 logic elements are utilized to implement this algorithm in an Altera cycloneH FPGA. The performance and resource consumption show that the design also suits for digital ASIC, which benefits in processing high volume of ECG data. © 2011 IEEE.

关键词： Wavelet transforms

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