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Universal Stability Criterion for Type-I Sampling Phase-Locked Loops

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2023年第4期70卷 1351-1355页

作者： Huang, Yunbo Chen, Yong Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME ECE FST Macau Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This brief reports a universal stability criterion for the type-I sampling phase-locked loop (S-PLL). The linear-time- variant model predicts with precision a maximum phase margin that decreases linearly with the increasing loop bandwidth (BW), leading to a maximum achievable loop BW that is half of the reference frequency. We verified the derived theory through extensive simulations and will present a guide that is useful in the design and optimization of different S-PLL schemes.

关键词： Voltage-controlled oscillators Phase locked loops Circuit stability Mathematical models Stability criteria Behavioral sciences Amplitude modulation Type-I sampling phase-locked loop (S-PLL) sub-sampling PLL (SS-PLL) voltage-controlled oscillator (VCO) linear time-variant (LTV) mode given phase margin (PM)

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A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Master-Slave S-PD Measuring 39.6-fsRMS Jitter,-260.2-dB FOM, and-70.96-dBc Reference Spur

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第4期70卷 1463-1475页

作者： Huang, Yunbo Chen, Yong Zhao, Bo Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI & IME ECE FST Taipa 999078 Macao Peoples R China Zhejiang Univ Inst VLSI Design Hangzhou 310027 Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This paper reports an active-buffer-free type-I sampling phase-locked loop (S-PLL). We innovate a fully-passive sampling phase detector with passive-gain multiplication after the sampler, resulting in a stably-boosted PD gain and better linearity. Together with a transformer-based rich-harmonic shaping voltage-controlled oscillator, the proposed S-PLL at 3.78 GHz exhibits an integrated jitter of 39.6 fs(RMS) (1 kHz to 100 MHz), and the jitter-power figure-of-merit scores -260.2 dB. The reference (REF) spur is -70.96 dBc due to the embedded REF-feedthrough suppression technique.

关键词： CMOS type-I sampling phase-locked loop (S-PLL) voltage-controlled oscillator (VCO) reference (REF) feedthrough suppression figure-of-merit (FOM) phase-detection gain (K-PD) sampling phase detector (S-PD)

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Arithmetic Progression Switched-Capacitor DC-DC Converter Topology With Soft VCR Transitions and Quasi-Symmetric Two-Phase Charge Delivery

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IEEE JOURNAL OF SOLID-state CIRCUITS 2022年第10期57卷 2919-2933页

作者： Jiang, Yang Law, Man-Kay Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI IME & FST ECE Macau Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This article presents an arithmetic progression (AP) switched-capacitor (SC) dc-dc converter topology for systematic step-down reconfigurable rational voltage conversion ratio (VCR) generation while exhibiting soft VCR transitions and quasi-symmetric two-phase charge delivery. The proposed AP topology features fixed steady-state voltage in all the flying capacitors ( $C_{{FLY}})$ irrespective of VCR change, essentially eliminating the internal $C_{{FLY}}$ hard-charging loss due to voltage rebalancing, effectively, improving the overall dynamic efficiency. It also achieves optimal steady-state slow-/fast-switching loss. Furthermore, due to the inherent quasi-symmetric output charge ( $Q_{{OUT}})$ delivery property in the two-phase switching operations, the proposed topology alleviates the VCR-dependent imbalanced per-phase $Q_{{OUT}}$ delivery to relax the $C_{{OUT}}$ requirement in a single-branch converter implementation. We propose a cross-coupled bootstrapping driver (XCBD) operated at half of the converter switching frequency ( $f_{{SW}})$ to adaptively control the flying power switches without relying on dual-branch interleaved architecture. Fabricated in 65-nm CMOS, the implemented AP chip prototype achieves a step-down VCR of 5:4/3/2/1 and converts a 1.5-V input to a 0.18-1.19-V output. With a measured steady-state peak power conversion efficiency (PCE) of 93.7%, this work can deliver a maximum output current of 400 mA while attaining an average conversion efficiency of up to 89% under a periodic VCR transition at 100 kHz as benefitted from the intrinsic soft VCR transition and low conduction loss properties.

关键词： Video recording Topology Steady-state Voltage Capacitors Switches Voltage control Bootstrapping driver charge sharing dc-dc converter reconfigurable soft transition switched-capacitor (SC) topology voltage conversion ratio (VCR)

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A 2.5-5-V Input 100-V Output 86.2% Peak Efficiency Fibonacci-Dickson Hybrid Converter for Acoustic Surface Audio Driver

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IEEE JOURNAL OF SOLID-state CIRCUITS 2025年

作者： Jiang, Yifan Lu, Yan Hu, Chen Jiang, Junmin Southern Univ Sci & Technol Dept Elect & Elect Engn Shenzhen 518055 Peoples R China Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau FST DECE Macau Peoples R China Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China

This article introduces a hybrid boost converter designed for the acoustic surface audio driver, operating within an input voltage range of 2.5-5 V and boosting it to a high voltage (HV) of 100 V. The proposed design adopts a cascaded approach by integrating the Fibonacci and Dickson switched-capacitor (SC) topologies. This combination enables the converter to achieve a high-voltage conversion ratio (VCR). It offers the advantages of a reduced number of flying capacitors and reduced voltage stress for power switches. To improve the overall efficiency, we only use laterally diffused N-type metal-oxide-semiconductor (LDNMOS) power switches, which offer low on-resistance, fast switching, and reduced fabrication mask requirements. In addition, a stacked active bootstrap replaces the conventional bootstrap diode with an actively controlled transistor that has lower on-resistance, overcoming the diode forward voltage drop issue and improving efficiency. The converter delivers a maximum output power of 2 W at 100-V output voltage with a peak efficiency of 86.2% and a power density of 7.43 W/cm(3).

关键词： Acoustic surface audio active bootstrap boost converter dc-dc converter Dickson Fibonacci high-voltage conversion ratio (VCR) hybrid converter laterally diffused N-type metal-oxide-semiconductor (LDNMOS) switched-capacitor (SC) converter SC power converter

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A High-Performance Dual-Topology CMOS Rectifier With 19.5-dB Power Dynamic Range for RF-Based Hybrid Energy Harvesting

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (vlsi) SYSTEMS 2023年第8期31卷 1253-1257页

作者： Choo, Alexander Ramiah, Harikrishnan Churchill, Kishore Kumar Pakkirisami Chen, Yong Mekhilef, Saad Mak, Pui-In Martins, Rui P. Univ Malaya Fac Engn Dept Elect Engn Kuala Lumpur 50603 Malaysia Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME ECE FST Macau Peoples R China

This brief reports a dual-topology CMOS rectifier with an extended power dynamic range (PDR) for radio frequency (RF)-based hybrid energy harvesting (RF-HEH) systems. By leveraging both the cross-coupled differential drive (CCDD) and the Dickson topologies with high forward conduction and low reverse leakage, we obtain an extension of the rectifier's PDR by adaptively disabling the CCDD counterpart and enabling the Dickson counterpart to dominate the rectifier's performance during high-power operation. Apart from that, we formulate a rectifier-performance index (RPI), which accounts for the power conversion efficiency (PCE), the PDR, the sensitivity, and the load resistance of the rectifier to provide an adequate performance benchmark with the state-of-the-art rectifiers. Fabricated in a 130-nm CMOS, the proposed dual-topology rectifier measures a wide PDR of 19.5 dB with a peak PCE of 78.4% for a 100-kO load operating at 900 MHz. Besides, our prototype records the highest RPI of 19.2 compared to the recent arts operating at GSM900.

关键词： Rectifiers Radio frequency Sensitivity Topology Threshold voltage Very large scale integration Energy harvesting Power conversion efficiency (PCE) power dynamic range (PDR) radio frequency (RF)-based hybrid energy harvesting (RF-HEH)

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A Single-Stage Bipolar-Output Regulating Rectifier With Negligible Cross-Regulation for Wireless Display

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IEEE JOURNAL OF SOLID-state CIRCUITS 2024年第9期59卷 2983-2994页

作者： Huang, Chenyu Zhan, Chenchang Bai, Xianglong Lu, Yan Univ Macau Inst Microelect State Key Lab Analog Mixed Signal VLSI Macau Peoples R China Univ Macau FST DECE Macau Peoples R China Southern Univ Sci & Technol Sch Microelect Shenzhen 518055 Peoples R China Southern Univ Sci & Technol Sch Microelect Shenzhen 518055 Peoples R China

This article presents a 6.78-MHz single-stage bipolar-output regulating (SSBOR) rectifier with symmetrical structure for active-matrix organic light-emitting diode (AMOLED) displays. The proposed full-wave rectifier converts ac power to positive and negative dc voltages through six on-chip switches. To handle high voltage stress, four power switches are stacked MOS as full-bridge rectifying transistors, while two single-NMOS switches are connected between the ac nodes and ground, providing paths for unequal load currents with low conduction loss. This high-integration structure improves power conversion efficiency and reduces chip area. Besides, since the ac current in the series-resonant LC tank varies little with different output loads, there would be negligible cross-regulation during transient response. Two independent pulsewidth modulation (PWM) and type-II compensation circuits work in each output feedback loop. Fabricated in 180-nm BCD process, using only 5-V devices, this proposed rectifier obtains +5-and -5-V bipolar outputs with a maximum of 500-mA output current each. The measurement results show 86.4% peak power conversion efficiency, less than 15-mu s transient recovery time and 103-mV overshoot/undershoot with 50-400-mA load steps, and unnoticeable cross-regulation.

关键词： Active rectifier bipolar output dual output positive and negative voltages receiver (RX) series resonant single-stage regulating rectifier wireless power transfer (WPT)

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A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter,-258.7-dB FOM, and-75.17-dBc Reference Spur

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (vlsi) SYSTEMS 2023年第2期31卷 188-198页

作者： Huang, Yunbo Chen, Yong Zhao, Bo Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME ECE FST Macau Peoples R China Zhejiang Univ Inst VLSI Design Hangzhou 310027 Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This article presents a low-jitter and low-spur type-II sampling phase-locked loop (S-PLL). The innovative introduction of a differential parallel-series double-edge sampling phase detector (S-PD) achieves a high phase-detection gain and reduces the S-PLL in-band phase noise (PN). Incorporating a transformer-based harmonic-rich shaping voltage-controlled oscillator (VCO), the proposed S-PLL prototyped in a 65-nm CMOS, operates at 3.6 GHz and scores an integrated jitter of 43.1 fsrms integrated from 1 kHz to 100 MHz, it also exhibits a jitter-power figure-of-merit (FOM) of -258.7 dB. The measured reference (REF) spur is -80.34 dBc at f(REF) and -75.17 dBc at 2 f(REF), respectively.

关键词： Phase locked loops Voltage-controlled oscillators Jitter Very large scale integration Topology Clocks Capacitors CMOS figure-of-merit (FOM) harmonic-rich voltage-controlled oscillator (VCO) integrated jitter phase-detection gain (KPD) reference (REF) feedthrough suppression sampling phase-locked loop (S-PLL) type-I type-II

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A 5.99-GHz VCO With Wideband-Differential-Mode Second Harmonic Resonance Achieving-138.9 dBc/Hz Phase Noise at an Offset of 10 MHz

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IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS 2024年第11期34卷 1267-1270页

作者： Yang, Chaowei Chen, Yong Huang, Yunbo Martins, Rui P. Mak, Pui-In Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME ECE FST Macau Peoples R China Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This article presents a voltage-controlled oscillator (VCO) with wideband-differential-mode (DM) second harmonic resonance. It features a single-turn multitap inductor plus a small tail resonator to boost the drain-to-gate voltage gain (AV). It also creates intrinsic-high-Q impedance peaks at the fundamental and double oscillation frequencies, which simultaneously achieves phase noise (PN) and 1/f(3 )PN-corner reduction. Prototyped in 65-nm CMOS, the 5.99-GHz VCO scores a -138.9 dBc/Hz PN at an offset of 10 MHz and consumes 3.17 mW of power with a 0.67 V supply. The achieved figure-of-merit (FoM) values were 177.5, 186.6, and 189.4 dBc/Hz at an offset of 0.1, 1, and 10 MHz, with a 1/f(3) PN corner of 400 kHz. Over a 14% tuning range (TR), without any additional harmonic tuning, the VCO upholds a consistent FoM > 189 dBc/Hz at an offset of 10 MHz. The core area is 0.465 mm(2).

关键词： 1/ f (3 )pn corner CMOS figure-of-merit (FoM) figure-of-merit (FoM) impulse sensitivity function (ISF) impulse sensitivity function (ISF) phase noise (PN) phase noise (PN) voltage-controlled oscillator (VCO) voltage-controlled oscillator (VCO) wideband-harmonic shaping wideband-harmonic shaping wideband-harmonic shaping

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A Reconfigurable CMOS Stack Rectifier With 22.8-dB Dynamic Range Achieving 47.91% Peak PCE for IoT/WSN Application

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (vlsi) SYSTEMS 2023年第10期31卷 1619-1623页

作者： Churchill, Kishore Kumar Pakkirisami Ramiah, Harikrishnan Choo, Alexander Chong, Gabriel Chen, Yong Mak, Pui-In Martins, Rui P. Univ Malaya Fac Engn Dept Elect Engn Kuala Lumpur 50603 Malaysia USM Analog & Logic IC Dept Nexperia Res & Dev Penang SAINS Bukit Jambu 11900 Malaysia Univ Macau State Key Lab Analog & Mixed Signal VLSI IME DECE FST Macau Peoples R China Univ Lisbon Inst Super Tecn P-1649004 Lisbon Portugal

This brief proposes a 900-MHz novel CMOS-reconfigurable stack rectifier (RSR) implemented in a three-stage cross-coupled differential rectifier (CCDR) for battery-assist Internet-of-Things (IoT)/wireless sensor network (WSN) applications. A three-mode RSR is incorporated for an extended dynamic range (DR) input power level with a 100-k Omega load, fabricated in the 130-nm CMOS. The realized RSR achieves a wide DR power conversion efficiency (PCE) by reducing the ON-resistance (RON) in the low-power zone (LPZ) achieved by reducing the threshold voltage (V-th) of the device and alternately increasing V-th in the high-power zone (HPZ) by implementing the proposed reconfigurable stack transistor technique along with the multithreshold voltage (MTV) technique. The circuit observes a measured result of 47.91% in peak PCE at an input power of -14 dBm by driving a 100-k Omega load. The proposed circuit also achieved 22.8 and 16.3 dB of DR with a PCE over 20% and 30%, respectively. Compared to other state-of-the-art designs, our work exhibits better DR and PCE.

关键词： xCMOS stack transistor dynamic range (DR) power conversion efficiency (PCE) multithreshold-voltage technique radio-frequency (RF) energy harvesting (EH) reconfigurable rectifier RF-DC converters

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A 0.11-pJ/Bit True Random Number Generator Based on a Clocked Current-Starved Inverter 17

A 0.11-pJ/Bit True Random Number Generator Based on a Clocke...

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17th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2024

作者： Cheng, Kai Yang, Chaowei Martins, Rui P. Mak, Pui-In Chen, Yong University of Macau State-Key Laboratory of Analog and Mixed-Signal VLSI IME/ECE-FST China Instituto Superior Técnico Universidade de Lisboa Lisboa1049-001 Portugal Department of Electronic Engineering Beijing100084 China

ISBN: (纸本)9798350361834

This paper presents a clocked current-starved inverter-based true random number generator (TRNG) in 65-nm CMOS. The design of the TRNG uses inverter noise amplification and quantification through a sense latch. We add two extra transistors to a regular inverter to construct a current-starved inverter, used to remove the bias of the raw TRNG sequence generated by charge injection and SL offset. An adaptive calibration algorithm in conjunction with successive approximation register logic provides the biasing to the clocked current-starved inverter. Our TRNG occupies an area of only 0.0026 mm2and scores an energy efficiency of 0.11 pJ/bit for a 10 Mb/s random sequence with a 0.5 V supply. It can operate efficiently across a 0.5-1.4 V. Our TRNG is able to pass all the National Institute of Standards and Technology tests without requiring post-processing. © 2024 IEEE.

关键词： CMOS integrated circuits

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