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IEEE Symposium on Radio Frequency Integrated Circuits (RFIC)

作者： Yue Wu Yatao Peng Benhao Huo Jun Yin Rui P. Martins Pui In Mak State Key Lab. of Analog and Mixed-Signal VLSI IME/ECE of FST University of Macau China Instituto Superior Técnico Universidade de Lisboa Portugal

ISBN: (数字)9798350359473

ISBN: (纸本)9798350359480

We reported a dual-core triple-mode voltage-controlled oscillator (VCO) to adapt to the low power consumption and large frequency tuning range (FTR) of the signal source in quantum interface systems. We proposed using only magnetic and inductive tuning elements for resonance splitting to construct the VCO’s triple-mode LC tank. This avoids the FTR sacrifice when using a conventional capacitive tuning element to build the multi-mode tank. To reduce the power consumption of the negative trans-conductance (-G M ) cells in the multicore multi-mode VCO, we proposed a structure that provides a triple oscillating mode with only two -G M cores. In addition, to overcome the deterioration of phase noise (PN) due to the switch-on resistances, we introduced a switching -GM technique for mode selection without using the MOSFET switches. The wideband VCO was specifically designed for cryogenic operation, utilizing a 28 nm CMOS technology. The measured results demonstrate an FTR of 7.1-15.7 GHz (75.4%) and a peak figure-of-merit (FoM) of 202.1 dBc/Hz at 3.7 Kelvin.

关键词： Phase noise Power demand Multicore processing Voltage-controlled oscillators Kelvin Switches Cryogenics

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A 12.87-dB Gain 10.5-dBm OPldB60-to-66-GHz LNA in 0.15-μm GaAs pHEMT Technology

A 12.87-dB Gain 10.5-dBm OPldB60-to-66-GHz LNA in 0.15-μm G...

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2022 IEEE the Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2022

作者： Li, Xuefeng Wang, Yuting Wu, Tianxiang Chen, Yong Ren, Junyan Ma, Shunli School of Microelectronics Fudan University State Key Laboratory of ASIC and System Shanghai China State Key Laboratory of ASIC and System School of Information Science and Technology Fudan University Shanghai China University of Macau State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST Macao China

ISBN: (纸本)9781665450690

This paper presents a V-band low noise amplifier (LNA) implemented in a 0.15-μm Gallium Arsenide (GaAs) pseudomorphic high electron-mobility transistor (pHEMT) technology. The LNA adopts a three-stage common-source (CS) topology. Each transistor has a bias circuit, and the microstrip-line inductor is used to realize the input noise matching network, the interstage, and the output matching network. Circuit simulations show that our LNA scores a 12.87-dB small-signal gain, the 3-dB bandwidth ranges from 60 GHz to 66 GHz, and the current consumption is 30 mA under a 5-V supply voltage. Its noise figure is 5.9 dB, and the output 1-dB compression point is 10.5 dBm. The chip area is 1.32× 1.5mm2. © 2022 IEEE.

关键词： Low noise amplifiers

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A Highly Integrated Tri-Path Hybrid Buck Converter With Reduced Inductor Current and Self-Balanced Flying Capacitor Voltage

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第9期69卷 3841-3850页

作者： Wang, Chuang Lu, Yan Martins, Rui P. Beijing Univ Posts & Telecommun Sch Elect Engn Beijing 100876 Peoples R China Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Taipa Macao Peoples R China Univ Macau FST DECE Taipa Macao Peoples R China Univ Lisbon Inst Super Tecn P-1049001 Lisbon Portugal

This paper presents a single-stage tri-path buck converter with reduced inductor current and self-balanced flying capacitor voltage. The proposed converter introduces capacitor paths to reduce the average inductor current and inductor current ripple, hence decreasing the conduction loss. Operating with two states per conversion cycle, it exhibits a relatively low voltage conversion ratio of D/(1 + 2D). Besides, it realizes a self-balanced flying capacitor voltage in the charge redistribution phase. Similar to the conventional buck converter, the proposed converter in continuous-current mode only has two complex poles. Therefore, we design a Type-III compensator to obtain a good transient response. Moreover, the circuit does not require extra supplies for gate drivers due to the reutilization of the flying capacitor voltages, eliminating additional circuit and power overheads. The proposed converter, validated in a 65-nm standard CMOS technology, regulates a 0.7 V - 1 V output voltage from a 3.3 V - 4 V input voltage, delivering a maximum output power of 270 mW. The peak efficiency is 84%, with a switching frequency up to 5 MHz.

关键词： DC-DC converter hybrid converter reduced inductor current flying capacitor voltage balancing low voltage conversion ratio highly-integrated Type-III compensation

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A SAW-less 3FLO-Suppression RF Transmitter with a Transformer-Based N-Path Switched-Capacitor Modulator Achieving -157.6dBc/Hz Output Noise and -61dBc CIM3

A SAW-less 3FLO-Suppression RF Transmitter with a Transforme...

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IEEE Symposium on Radio Frequency Integrated Circuits (RFIC)

作者： Gengzhen Qi Haonan Guo Pui-In Mak Yunchu Li School of Microelectronics Science and Technology Sun Yat-Sen University China State-Key Lab. of Analog and Mixed-Signal VLSI/IME and FST-ECE University of Macau China

ISBN: (数字)9798350359473

ISBN: (纸本)9798350359480

This paper reports a SAW-less RF transmitter with a passive-intensive I/Q modulator. Specifically, without the noisy and nonlinear transconductor (g m ), our proposed linear I/Q modulator features a transformer-based N-path switched-capacitor (SC) topology to enable high-Q bandpass filtering at a flexible RF, rejecting the out-of-band (OB) noises in baseband (BB) and the modulator. The intrinsic lowpass characteristic of the transformer also reduces the harmonic terms at 3xf LO at the output of the modulator, thereby effectively suppressing CIM 3 . For the power amplifier (PA) driver, it is aided by a paralleled-g m linearizer to improve the performance. Prototyped in a 65nm CMOS process, our transmitter manifests a consistently low OB noise (≤-157dBc/Hz) for 2 to 3GHz. Under a 2.3dBm output power, the transmitter shows a high transmitter efficiency (5.1%) and a high linearity (CIM 3 <-60dBc and ACLR 1 <-46dBc). The power consumption is 32.5mW at 2.5GHz, and the active area is 0.21mm 2 .

关键词： Radio frequency Radio transmitters Noise Modulation Power amplifiers Linearity Switches

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A 23-nA Quiescent Current Output-Capacitorless LDO Regulator for IoT Devices

A 23-nA Quiescent Current Output-Capacitorless LDO Regulator...

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International Conference on ASIC

作者： Shengnan Zhou Xiangyu Mao Cheng Huang Rui P. Martins Yan Lu State Key Laboratory of Analog and Mixed-Signal VLSI Institute of Microelectronics and FST-DECE University of Macau Macao China Department of Electrical and Computer Engineering Iowa State University Ames USA

This paper presents an ultra-low quiescent current output-capacitorless low dropout regulator (OCL-LDO) with fast transient response. We design a rail-to-rail error amplifier with improved adaptive biasing, which provides a limited bias current at heavy load for better load regulation. The buffer with adaptive biasing and almost zero input-output voltage shift and embedded body-bias, combines the error amplifier and the gate of M P . The proposed LDO is designed in a 65-nm CMOS process. Simulation result shows that the proposed LDO consumes a quiescent current of only 23 nA at a supply voltage of 0.8 V. The voltage undershoot is 98 mV during a 20-mA maximum load transient. And we obtain a FOM T of 0.00023 ps.

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A Switched-Capacitor Single-Inductor Multiple-Output Dual-Path Hybrid DC-DC Converter With Path-Sharing Technique

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ELECTRONICS LETTERS 2025年第1期61卷

作者： Li, Yang Huang, Mo Martins, Rui P. Lu, Yan Univ Macau State Key Lab Analog & Mixed Signal VLSI Inst Microelect Macau Peoples R China Univ Macau DECE FST Macau Peoples R China Tsinghua Univ Dept Elect Engn Beijing Peoples R China

Single-inductor multiple-output (SIMO) DC-DC converters face the challenges of large inductor current, discontinuous charge to each output and poor self-regulation. This design proposes a switched-capacitor SIMO dual-path hybrid converter that can reduce the inductor volume and output ripple by taking the advantages of hybrid dual-path structure. The proposed path-sharing topology improves the transient response of the in-transient channel. This work, designed in a 0.18-mu m BCD process, reveals in the simulation that the cross-regulation is 20 mV/A and the self-regulation is 87 mV/A with a 1A load step. The simulated peak efficiency is 94.3% and maximum output ripple is 24 mV.

关键词： power electronics energy conversion and sustainability power convertors

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Short-Term Power Load Forecasting Using MOGOA and ConvBiLSTM During COVID-19 Pandemic

Short-Term Power Load Forecasting Using MOGOA and ConvBiLSTM...

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2023 International Conference on Power System Technology, PowerCon 2023

作者： Xu, Da Liu, Bowen Lam, Chi-Seng Huang, Zhangyou University of Macau State Key Laboratory of Analog and Mixed-Signal Vlsi Macao China Institute of Microelectronics University of Macau Macao China School of Automation China University of Geosciences Wuhan430074 China University of Macau Fst Department of Electrical and Computer Engineering Macao China

ISBN: (纸本)9798350300222

Due to the high restrictions of the global COVID-19 on society, economy and production, the electrical supply-demand balance is facing a great challenge. This paper proposes a short-term load forecasting (STLF) method based on multi-factor fusion during the COVID-19. After fully analyzing and screening the nonlinear coupling interactions among cross-domain weather and public health safety features, a convolutional bi-directional long short-term memory neural network (ConvBiLSTM) is developed based on the convolutional and bidirectional loop enhancements of long short-term memory (LSTM). To avoid early termination of training the global optimal solution, multi-objective grasshopper optimization algorithm (MOGOA) is adopted to select the inherent hyperparameters of the forecasting network. Attention mechanism is further introduced to enhance the learning ability of the key features in temporal data, improving the forecasting accuracy and robustness of ConvBiLSTM. Comparisons on cross-domain COVID-19 dataset over classical methods are performed to verify its effective and superior performances. © 2023 IEEE.

关键词： Coronavirus

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A 26-38GHz Ultra-Wideband Balanced Frequency Doubler in 0.15μm GaAs pHEMT Process

A 26-38GHz Ultra-Wideband Balanced Frequency Doubler in 0.15...

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IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

作者： Liu, Wenyang Wu, Tianxiang Yan, Tianyang Yang, Fan Chen, Yong Ma, Shunli Fudan Univ Sch Microelectronicsline State Key Lab ASIC & Syst Shanghai Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI Taipa Macao Peoples R China Univ Macau IME ECE FST Taipa Macao Peoples R China

ISBN: (纸本)9781665450737

This paper reports the analysis and design of a 26-38GHz balanced frequency doubler. The balanced frequency doubler eliminates odd harmonics by using the characteristics of the circuit. We employ a cascade of two-stage amplifiers to increase output power, and a transformer-based magnetic-coupled resonator (MCR) matching technique to widen the bandwidth. Besides, the transformer can realize the single-ended to differential conversion without penalizing additional power consumption. The frequency doubler is designed in a 0.15 mu m GaAs pHEMT process. Post-layout simulation results show that the output power is greater than 10dBm over 26-38GHz, and the fundamental-to-harmonic suppression is greater than 15 dBc. The DC power consumption is 23 mA at a 5-V supply. The chip area is 0.75x1.55 mm(2)

关键词： balanced frequency doubler magnetic-coupled resonator (MCR) mmWave output power GaAs

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analog and mixed-signal CMOS Circuits: The emergence and leadership of a Lab, a reference Book and the future at the core of the A/D Interface in the IoE

Analog and Mixed-Signal CMOS Circuits: The emergence and lea...

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European Conference on Solid-state Circuits (ESSCIRC)

作者： Rui P. Martins State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST University of Macau Macau China Instituto Superior Técnico Universidade de Lisboa Lisboa Portugal

The analog/Digital Interface with Audio, Vision & Sensors, is essential for the Internet of Everything -IoE. The state key laboratory of analog and mixed-signal vlsi from University of Macau (UM), with a history of 30+ years, emerged as such in 2011, being now world-renowned for its excellence in the design of innovative circuits for the analog/digital interface. In a recent book entitled analog and mixed-signal Circuits in Nanoscale CMOS, we presented the most critical building blocks of such interface that need to exhibit high quality performance with low power consumption, high energy-efficiency and high speed. There is a huge pressure in the design area with a high demand for analog design engineers, opening a vast field of opportunities and challenges that imply a continuous knowledge update. UM is contributing to stimulate and well-equip the mind of future skillful analog design engineers in state-of-the-art designs adequate for most IoE applications.

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A 3.52-GHz Harmonic-Rich-Shaping VCO with Noise Suppression and Circulation, Achieving-151-dBc/Hz Phase Noise at 10-MHz Offset 53

A 3.52-GHz Harmonic-Rich-Shaping VCO with Noise Suppression ...

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IEEE International Symposium on Circuits and Systems (IEEE ISCAS)

作者： Huang, Yunbo Chen, Yong Mak, Pui-In Martins, Rui P. Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME ECE FST Macau Peoples R China

ISBN: (纸本)9781728192017

This paper presents a transformer-based harmonic-rich-shaping voltage-controlled oscillator (VCO). Its active core features noise suppression and circulation to improve the phase noise (PN) performance, and its 2:2 transformer allows a very short common-mode (CM) return path without sacrificing the tank's quality factor. The proof-of-concept prototype is a 3.52-GHz VCO in 65-nm CMOS. It scores a -151-dBc/Hz PN at 10-MHz offset, and consumes 6.77 mW of power at a 0.7-V supply. The achieved Figure-of-Merit (FOM) is 187.8/192.3/193.7 dBc/Hz at 0.1/1/10-MHz offsets, with a 1/f(3) PN corner of 220 kHz. Over a 22.1% tuning range, the VCO upholds a consistent FOM of >193.3 dBc at 10-MHz offset, and a 1/f(3) PN corner of <250 kHz. It has a very low supply pushing of -10 and 37 MHz/V at the lowest and highest frequencies, respectively. The core area is 0.33 mm(2).

关键词： CMOS noise suppression and circulation voltage-controlled oscillator (VCO) phase noise (PN) flicker (1/f) noise thermal noise noise transfer harmonic rich shaping impulse sensitivity function (ISF) 1/f(3) PN corner Figure-of-Merit (FOM) tuning range (TR) transformer supply pushing quality factor

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