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An 80W Single-Inductor DC-DC Architecture for Simultaneous Flash Charging and Dual-Output PoL Supply with 92.1% Peak Efficiency from 15V-to-28V Input to 12.6V/3.3V/1V Outputs Using 1.3mm3 Inductor

An 80W Single-Inductor DC-DC Architecture for Simultaneous F...

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European Conference on Solid-state Circuits (ESSCIRC)

作者： Xiongjie Zhang Anyang Zhao Xinman Li Yang Jiang Rui P. Martins Pui-In Mak State Key Laboratory of Analog and Mixed-Signal VLSI IME University of Macau Macau China Instituto Superior Técnico Universidade de Lisboa Lisbon Portugal

ISBN: (数字)9798350388138

ISBN: (纸本)9798350388145

This paper presents a high-density DC-DC power delivery (PD) scheme using the proposed synergetic PD architecture (SyPoDA), enabling simultaneous 3-cell Li-ion battery charging under USB PD 3.2 protocol and single-inductor dual-output (SIDO) point-of-load (PoL) supplies. The proposed SyPoDA synergizes a switched-capacitor (SC) flash charger with our proposed hybrid SIDO converter, featuring 1) power stage sharing along charging and load-supply paths, 2) constant inductor DC current ($I_{L, D C}$) reduction at the PoL side, and 3) uninterrupted steady-state SIDO output current. It can improve the utilization of the high-voltage part power stage, reduce the inductor size, and lower the output capacitor (Co) requirement, improving the total power density. In circuit design, we propose a pulse-current-based gate driver (PCGD) circuit for monolithic GD integration. Fabricated in a 180-nm BCD process, the proposed SyPoDA prototype within a total 3D volume of $117 \mathrm{~mm}^{3}$ achieves a $92.1 \%$ peak efficiency at 42 W total output when converting a 15-to-28-V input to three outputs of $12.6 \mathrm{~V} / 3.3 \mathrm{~V} / 1 \mathrm{~V}$. It supports a maximum output power of 80 W.

关键词： Power system measurements Three-dimensional displays Density measurement Switches Gate drivers Universal Serial Bus Hybrid power systems System-on-chip Steady-state Inductors

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An accelerated architecture of change-point detection for FMCW radar mutual interference based on FPGA

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2021年第11期49卷 3719-3732页

作者： Yang, Siyuan Li, Songyi Wu, Jiayan Chen, Yong Liu, Zhenyu Guangdong Univ Technol Sch Informat Engn Guangzhou 510006 Peoples R China Univ Macau State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau IME ECE FST Macau Peoples R China

The mutual interference between frequency modulated continuous wave (FMCW) radars seriously affects autonomous driving. The interference will cause a short-duration pulse-like signal, which contains several change points in the time domain. The change-point detection method called bottom-up segmentation (BOTUP) is applied to deal with a short duration pulse-like signal, which has excellent detection accuracy. However, the serial processing of BOTUP will cause considerable delay, which is not conducive to real-time detection of automatic driving. In this paper, an accelerated architecture of BOTUP (ACC-BOTUP) based on field-programmable gate array (FPGA) is proposed. As BOTUP has segmented characteristics and without data dependency between the cost functions, a parallel structure is proposed to reduce the latency. Further, a pipeline structure is proposed to execute the operations of the cost functions in an overlapping manner. Compared with the original BOTUP (O-BOTUP), the latency of ACC-BOTUP is reduced by 82%, which is more suitable for real-time detection in autonomous driving.

关键词： bottom-up segmentation change-point detection FMCW radar FPGA mutual interference

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A switched-capacitor-assisted wireless power transfer system with regulating TX power and fast global loop

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ELECTRONICS LETTERS 2022年第12期58卷 477-479页

作者： Huang, Chenyu Lu, Yan Zhan, Chenchang Martins, Rui P. Univ Macau State Key Lab Analog Mixed Signal VLSI Inst Microelect Taipa Macao Peoples R China Univ Macau DECE FST Taipa Macao Peoples R China Southern Univ Sci & TechnNol Sch Microelect Shenzhen Peoples R China Minist Educ Engn Res Ctr Integrated Circuits Next Generat Com Shenzhen Peoples R China

Wireless power transfer systems demand a regulating transmitter (TX) for global loop control and also a regulating receiver (RX) for its local loop. This design broadens the TX output power range, by merging a switched capacitor (SC) circuit with only 3 switches and 1 flying capacitor to boost the output power of the Class-D power amplifier. In addition, the transmitting power can be regulated by the duty ratio of the SC, improving the end-to-end power transfer efficiency under different load conditions. Moreover, the system obtains fast load transient response, with the help of a light-to-heavy load transient enhancement scheme in the TX and the hysteretic control in the RX. Designed in a 0.18-mu m BCD process, this work achieves 3.1 W maximum RX output power, 67.6% peak total efficiency, and 50 mu s response time during the light-to-heavy load transient simulation.

关键词： TX output power range TX power fast global loop load transient response end-to-end power transfer efficiency BIMOS integrated circuits radio receivers flying capacitor switched-capacitor-assisted wireless power transfer system radio transmitters light-to-heavy load transient enhancement scheme regulating transmitter switched capacitor networks inductive power transmission regulating receiver transmitting power switched capacitor circuit power amplifiers light-to-heavy load transient simulation global loop control wireless power transfer systems local loop transient response Class-D power amplifier capacitors

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A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common-Mode Resonator and Intrinsic Differential 2nd-Harmonic Output

A 9.97-GHz 190.6-dBc/Hz FOM CMOS VCO Featuring Nested Common...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Yunbo Huang Yong Chen Chaowei Yang Pui-In Mak Rui P. Martins State Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST University of Macau Macao China On leave from Instituto Superior Técnico Universidade de Lisboa Portugal

This paper presents an 8-to-10GHz CMOS voltage-controlled oscillator (VCO) with common-mode (CM) resonance. It features a nested 8-shape inductor-based CM resonator with intrinsic differential $2^{\text{nd}}$ harmonic extraction. The mutual coupling of the main tank and CM resonator is negligible due to the reversal magnetic field, which avoids the additional chip area occupation of the explicit CM inductor. The VCO prototyped in 65-nm CMOS scores a −136.7-dBc/Hz PN with 10-MHz offset at 9.97 GHz, consuming 4 mW of power with a standard supply voltage of 1-V. The achieved peak Figure-of-Merit (FOM) is 190.6 dBc/Hz at 10-MHz offsets. Over a 22.9% tuning range, the VCO upholds a consistent FOM of >188.5 dBc at a 10-MHz offset. The core area is 0.116 mm 2 ,

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A Hybrid Single-Inductor Bipolar-Output DC-DC Converter With Floating Negative Output for AMOLED Displays

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IEEE JOURNAL OF SOLID-state CIRCUITS 2021年第9期56卷 2760-2769页

作者： Mao, Fangyu Lu, Yan Bonizzoni, Edoardo Boera, Filippo Huang, Mo Maloberti, Franco Martins, Rui P. Univ Macau Inst Microelect State Key Lab Analog & Mixed Signal VLSI Macau 999078 Peoples R China Univ Macau DECE FST Macau 999078 Peoples R China Univ Pavia Dept Elect Comp & Biomed Engn I-27100 Pavia Italy

This article presents a hybrid single-inductor bipolar-output (SIBO) dc-dc converter for active-matrix organic light-emitting diode (AMOLED) displays, which are relatively more sensitive to the supply noise on the positive supply. First, to improve the display quality we adopt a floating negative output configuration to migrate all the switching ripples into the negative output, achieving a near-zero voltage ripple on the positive output. Second, we design low-power shunt regulators, which only deal with a small portion of the output ripple, to regulate the positive output voltage further, improving the load transient response. Besides, the hybrid topology and the proposed cross-coupled bootstrap- based level-shifter, with a dual-PMOS inverter buffer, only uses standard CMOS devices without deep-n-well, reducing the chip area and cost. The proposed converter, implemented in 0.35-mu m CMOS with 5-V devices, operates at 1 MHz, leading to a measured positive output voltage ripple lower than 1 mV (all conditions). It achieves a measured 3-mV undershoot voltage and, an unnoticeable overshoot voltage on the positive output, when the output current varies between 30 and 350 mA. The measured peak power efficiency is 89.3% at 1.1-W output power. The maximum output power is 3.5 W.

关键词： AMOLED display bipolar output dual-PMOS inverter floating negative output hybrid converter shunt regulator single-inductor multiple-output (SIMO)

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L${}_{\text{2}}$min${}^{\text{2/2s}}$: Efficient Linear Reconstruction Filter for Incremental Delta-Sigma ADCs

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IEEE Transactions on signal Processing 2023年 71卷 3229-3241页

作者： Bo Wang Man-Kay Law Jens Schneider College of Science and Engineering Hamad Bin Khalifa University Doha Qatar State Key Laboratory of Analog and Mixed-Signal VLSI Institute of Microelectronics and FST-ECE University of Macau Macau China

While it becomes more challenging to improve the energy efficiency of incremental delta-sigma data converters (IDCs) from the analog circuit design perspective, we propose two novel linear reconstruction filters for IDCs to enhance their performance in a digital way, including the L ${}_{\mathbf{2}}$ min ${}^{\mathbf{2}}$ filter and its symmetric version, the L ${}_{\mathbf{2}}$ min ${}^{\mathbf{2s}}$ filter. Compared to the classical linear reconstruction filters, such as the cascade-of-integrators (CoI) and cascaded integrator-comb (CIC) filter (an implementation of sinc filter), the proposed filters can achieve efficient quantization and thermal noise suppression, with the lowest thermal noise penalty factor of 1.2 among the high-order linear reconstruction filters. In this paper, we present analytical, numerical, and experimental results to demonstrate the superior performance of the filters for first-order and second-order IDC output reconstruction. The proposed filters are hardware-friendly and example digital implementations in a standard complementary metal-oxide-semiconductor (CMOS) and field-programmable gate array (FPGA) platforms are included in this paper.

关键词： Nonlinear filters Maximum likelihood detection Digital filters Quantization (signal) Filtering algorithms Modulation Noise reduction

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A 1-V 4-mW Differential-Folded Mixer With Common-Gate Transconductor Using Multiple Feedback Achieving 18.4-dB Conversion Gain,+12.5-dBm IIP3, and 8.5-dB NF

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (vlsi) SYSTEMS 2020年第5期28卷 1164-1174页

作者： Vitee, Nandini Ramiah, Harikrishnan Mak, Pui-In Yin, Jun Martins, Rui P. Univ Malaya Fac Engn Dept Elect Engn Kuala Lumpur 50603 Malaysia Univ Macau DECE FST State Key Lab Analog & Mixed Signal VLSI IME Macau Peoples R China

This article reports a novel differential-folded mixer with multiple-feedback techniques for performance enhancement. Specifically, we introduce the capacitor cross-coupled (CCC) common-gate (CG) transconductance stage to improve the noise figure (NF) at low power by boosting the effective transconductance, while enhancing the linearity via suppressing the second-order harmonic distortion. Typically, the created loop gain of the CCC can raise the third-order intermodulation (IM3) distortion, penalizing the input-referred third-order intercept point (IIP3). Here, we propose a positive and a second capacitive feedback into the CCC CG transconductor, not only to suppress the IM3 distortion current but also adds in design flexibility to the input transistors. Furthermore, the positive feedback also improves the input impedance matching, conversion gain, and NF through a flexible design criterion. Prototyped in a 0.13- \mu \text{m} process, the proposed mixer operating at 900 MHz dissipates 4 mW at 1 V. The measured double sideband (DSB) NF is 8.5 dB, the conversion gain ( G_{C} ) is 18.4 dB and the IIP3 is +12.5 dBm.

关键词： Capacitive feedback CMOS high linearity mixer positive feedback third-order intercept point (IIP3) third-order intermodulation (IM3) cancellation

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A 124–152 GHz > 15-dBm $\mathbf{P}_{\text{sat}}$ 28-nm CMOS PA Using Chebyshev Artificial- Transmission-Line-Based Matching for Wideband Power Splitting and Combining

A 124–152 GHz > 15-dBm $\mathbf{P}_{\text{sat}}$ 28-nm CMOS...

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IEEE Symposium on Radio Frequency Integrated Circuits (RFIC)

作者： Jincheng Zhang Tianxiang Wu Yong Chen Junyan Ren Shunli Ma State Key Laboratory of ASIC &#x0026 System Fudan University China State-Key Laboratory of Analog &#x0026 Mixed-Signal VLSI IME/ECE-FST University of Macau China

ISBN: (数字)9781665496117

ISBN: (纸本)9781665496124

This paper presents a 124–152 GHz power amplifier (PA) with >15 dBm saturation output power $(\mathbf{P}_{\text{sat}})$ in a 28-nm CMOS process. Low-coupling transformer-based fourth-order matching networks are used to extend the bandwidth (BW) with low insertion loss and compact area. A four-way Chebyshev-type artificial-transmission-line-based power combiner is proposed to further improve the output power without sacrificing BW. The measurement results show that this P A can achieve a peak gain of 22.6 $\mathbf{dB}$ with 28 GHz 3-dB BW. The in-band $\mathbf{P}_{\mathbf{sat}}$ is >15 dBm with a maximum output power of 16.2 dBm at 135 GHz. The total area of the chip is $\mathbf{0.66}\mathbf{\times}\mathbf{0.73}\ \mathbf{mm}^{\mathbf{2}}$ •

关键词： Semiconductor device measurement Power combiners Power amplifiers Radar Chebyshev approximation Radiofrequency integrated circuits Circuit faults

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A 3 THz CMOS Image Sensor

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IEEE JOURNAL OF SOLID-state CIRCUITS 2024年第9期59卷 2934-2947页

作者： Liu, Min Cai, Ziteng Wang, Zhe Zhou, Shaohua Law, Man-Kay Liu, Jian Ma, Jianguo Wu, Nanjian Liu, Liyuan Chinese Acad Sci Inst Semicond State Key Lab Superlatt & Microstruct Beijing 100083 Peoples R China Univ Chinese Acad Sci Coll Mat Sci & Optoelect Technol Beijing 100049 Peoples R China Zhejiang Lab Res Ctr Intelligent Chips & Devices Hangzhou 311121 Peoples R China Univ Macau Fac Sci & Technol FST ECE Dept Elect & Comp Engn State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau Inst Microelect IME Macau Peoples R China Univ Chinese Acad Sci Sch Elect Elect & Commun Engn Beijing 100049 Peoples R China

This article presents a 3 THz CMOS image sensor (Tera-CIS). The sensor has a column-parallel readout (CPRO) architecture that integrates an antenna-coupled pixel array and CPRO circuit chains on a monolithic chip. The proposed compact two-transistor (2T) pixel adopts a step-covered patch antenna and a defected ground structure (DGS) to obtain sufficient sensitivity and bandwidth. The step-covered patch antenna model is developed to predict pixel performances precisely. The DGS structure suppresses mutual coupling among adjacent pixels and shrinks the pixel pitch. In the CPRO circuit chain, chopping and oversampling techniques are employed to reduce noise and flexibly balance the dynamic range (DR) characteristics with the imaging rate. A digital decimation filter (DDF) with a time-multiplexing fashion is adopted to alleviate resource pressure. A 16.4k-pixel Tera-CIS was fabricated with a standard 0.18 mu m CMOS process. A 3 THz imaging platform with four different continuous-wave (CW) terahertz quantum cascade lasers was established. The pixel sensitivity was 753 V/W at 3.4 THz, with a measured detection bandwidth of 0.78 THz (from 3.08 to 3.86 THz). The DR in the voltage domain of the sensor reached 73 dB at 8 fps while the maximum DR in the power domain was 39.8 dB. Meanwhile, the sensor can operate up to 130 fps. The imaging system can achieve high-resolution imaging and clearly identify concealed objects.

关键词： Column-parallel readout (CPRO) architecture CPRO circuit chain defected ground structure (DGS) digital decimation filter (DDF) step-covered patch antenna terahertz CMOS image sensor (Tera-CIS) time-multiplexing

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A 0.11-pJ/Bit True Random Number Generator Based on a Clocked Current-Starved Inverter

A 0.11-pJ/Bit True Random Number Generator Based on a Clocke...

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International Conference on Solid-state and Integrated Circuit Technology

作者： Kai Cheng Chaowei Yang Rui P. Martins Pui-In Mak Yong Chen State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST University of Macau Macao China Instituto Superior Técnico Universidade de Lisboa Lisboa Portugal (Now) Department of Electronic Engineering Tsinghua University Beijing China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

This paper presents a clocked current-starved inverter-based true random number generator (TRNG) in 65-nm CMOS. The design of the TRNG uses inverter noise amplification and quantification through a sense latch. We add two extra transistors to a regular inverter to construct a current-starved inverter, used to remove the bias of the raw TRNG sequence generated by charge injection and SL offset. An adaptive calibration algorithm in conjunction with successive approximation register logic provides the biasing to the clocked current-starved inverter. Our TRNG occupies an area of only 0.0026 mm 2 and scores an energy efficiency of 0.11 pJ/bit for a 10 Mb/s random sequence with a 0.5 V supply. It can operate efficiently across a 0.5-1.4 V. Our TRNG is able to pass all the National Institute of Standards and Technology tests without requiring post-processing.

关键词： Voltage NIST Throughput Inverters Generators Energy efficiency Robustness Calibration Transistors Random sequences

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