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An 80W Single-Inductor DC-DC Architecture for Simultaneous Flash Charging and Dual-Output PoL Supply with 92.1% Peak Efficiency from 15V-to-28V Input to 12.6V/3.3V/1V Outputs Using 1.3mm3 Inductor

An 80W Single-Inductor DC-DC Architecture for Simultaneous F...

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European Conference on Solid-state Circuits (ESSCIRC)

作者： Xiongjie Zhang Anyang Zhao Xinman Li Yang Jiang Rui P. Martins Pui-In Mak State Key Laboratory of Analog and Mixed-Signal VLSI IME University of Macau Macau China Instituto Superior Técnico Universidade de Lisboa Lisbon Portugal

ISBN: (数字)9798350388138

ISBN: (纸本)9798350388145

This paper presents a high-density DC-DC power delivery (PD) scheme using the proposed synergetic PD architecture (SyPoDA), enabling simultaneous 3-cell Li-ion battery charging under USB PD 3.2 protocol and single-inductor dual-output (SIDO) point-of-load (PoL) supplies. The proposed SyPoDA synergizes a switched-capacitor (SC) flash charger with our proposed hybrid SIDO converter, featuring 1) power stage sharing along charging and load-supply paths, 2) constant inductor DC current ($I_{L, D C}$) reduction at the PoL side, and 3) uninterrupted steady-state SIDO output current. It can improve the utilization of the high-voltage part power stage, reduce the inductor size, and lower the output capacitor (Co) requirement, improving the total power density. In circuit design, we propose a pulse-current-based gate driver (PCGD) circuit for monolithic GD integration. Fabricated in a 180-nm BCD process, the proposed SyPoDA prototype within a total 3D volume of $117 \mathrm{~mm}^{3}$ achieves a $92.1 \%$ peak efficiency at 42 W total output when converting a 15-to-28-V input to three outputs of $12.6 \mathrm{~V} / 3.3 \mathrm{~V} / 1 \mathrm{~V}$. It supports a maximum output power of 80 W.

关键词： Power system measurements Three-dimensional displays Density measurement Switches Gate drivers Universal Serial Bus Hybrid power systems System-on-chip Steady-state Inductors

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A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter

A Self Bias-flip Piezoelectric Energy Harvester Array withou...

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Custom Integrated Circuits Conference (CICC)

作者： Zhen Li Zhiyuan Chen Man-Kay Law Sijun Du Xu Cheng Xiaoyang Zeng Jun Han State Key Laboratory of ASIC and System Fudan University Shanghai China State Key Laboratory of Analog and Mixed-Signal VLSI University of Macau Macau China Department of Microelectronics Delft University of Technology Delft Netherlands

With the advent of the lnternet-of-Things (1oT) era, sensor nodes are required in almost all fields to achieve a better interaction between humans and the environment. Piezoelectric energy harvester (PEH), which exhibits an equivalent electrical model of an AC current source /P in parallel with the inherent capacitor C P , is a promising technology to resolve the energy problem of such sensor nodes. Recently, inductor-based rectifiers, capacitor-based rectifiers and hybrid rectifiers have been proposed to improve the energy extraction efficiency of PEH devices [1]–[5]. However, these structures all require the aid of additional capacitors or inductors to achieve bias-flip operation, as illustrated in Fig. 1. These extra passive devices are typically large, which can be a major bottleneck in system-volumeconstrained applications such as MEMS [4]. In response to the above problem, this work proposes a novel 8-phase self bias-flip PEH interface with charge recycling and reusing (SBFRR). By using the C P of 4 PEHs as flipping capacitors, this scheme achieves a high voltage flipping efficiency without using extra energy reservoirs. The 4 C P can also serve as flying capacitors to achieve switched-PEH DC-DC (SPDC) conversion for MPPT, while maintaining a MOPIR of >3.5× with a PEH input voltage (V p ) from 0. 78Vto4.9V.

关键词： Micromechanical devices Capacitors Rectifiers Voltage Switches High-voltage techniques Reservoirs

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Demystifying Hybrid DC-DC Converters Using an Improved Transformer Model

TechRxiv

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TechRxiv 2023年

作者： Huang, Mo Hu, Tingxu Lu, Yan Martins, Rui P. The State Key Laboratory of Analog and Mixed-Signal VLSI Institute of Microelectronics FST-ECE University of Macau China Instituto Superior Técnico Universidade de Lisboa Lisbon1049-001 Portugal

Multiple hybrid DC-DC converter topologies emerged to achieve better efficiency and power density for various applications. However, it is unclear how these topologies evolve from the original DC model. Therefore, it would be difficult to intuitively understand the pros and cons of the topologies only from the circuit level point-of-view. In this work, we propose an improved transformer model for hybrid converters. The proposed model demystifies the converters, explaining how they evolve, and how such evolution affects efficiency and other performances. Meanwhile, we can directly predict the important features of the converters from the proposed model, such as the working principles, conversion ratio, switch stress, inductor currents balance/equalization, switch loss, switching node voltage changing times, and flying capacitor voltage balance. To verify the effectiveness of the proposed model we utilize it in six popular hybrid converters. © 2023, CC BY-NC-SA.

关键词： DC-DC converters

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Cross-paradigm data alignment to improve the calibration of asynchronous BCI systems in EEG-based speech imagery

Cross-paradigm data alignment to improve the calibration of ...

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Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

作者： Mingtao Li Sio Hang Pun Fei Chen State Key Laboratory of Analog and Mixed Signal VLSI University of Macau Macau China Department of Electrical and Electronic Engineering Southern University of Science and Technology Shenzhen China

ISBN: (数字)9798350371499

ISBN: (纸本)9798350371505

The brain-computer interfaces (BCIs) based on speech imagery with asynchronous (self-paced) paradigms enable users to directly access and manipulate BCIs with more freedom. Compared with the indirect BCIs with traditional synchronous (cue-based) paradigms, the calibration time of asynchronous paradigms was much longer and with the unbalanced number of task states and idle states. This work aimed to improve the calibration of asynchronous BCI systems by applying a data alignment (DA) approach on cue-based and self-paced paradigms. The cue-based paradigm was regarded as the calibration paradigm and the self-paced paradigm was the testing paradigm. The data alignment approach based on the parallel transport mapped their features on the same tangent space. The logistic regression was used as the classifier to classify task states and idle states. The average result with DA was 7.52% higher than that without DA (baseline), which were 78.45% and 70.92%, respectively. Specially, the best classification accuracy was for 91.82% with DA, and the largest improvement in accuracy was 22.92%. These results suggest that it is practical to use a synchronous paradigm as calibration paradigm in asynchronous BCI systems and the data alignment approach has positive impacts on the classification of task states and idle states.

关键词： Logistic regression Accuracy Electroencephalography Brain-computer interfaces Calibration Engineering in medicine and biology Testing

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Improved Dead-Beat Control for Single-Phase LC-Coupling Hybrid Active Power Filter (LC-HAPF)

Improved Dead-Beat Control for Single-Phase LC-Coupling Hybr...

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IEEE International Symposium on Industrial Electronics (ISIE)

作者： Pak-Ian Chan Wai-Kit Sou Chi-Seng Lam State Key Laboratory of Analog and Mixed-Signal VLSI University of Macau Macao China Institute of Microelectronics University of Macau Macao China Department of Electrical and Computer Engineering University of Macau Macao China

In this paper, an improved dead-beat controller (DBC) for a single-phase LC-coupling hybrid active power filter (LC-HAPF) is proposed to achieve both low steady-state error and fast transient response. The conventional DBC has an inherent discretized and predictive error, which can increase the steady-state error. Thus, a signal correction technique is used to reduce the steady-state error. Moreover, the improved DBC is implemented with a coupling capacitor voltage observer to replace the voltage sensor, thus reducing the system cost. After that, the stability analysis and parameter design of the proposed improved DBC for the LC-HAPF are given in detail. Subsequently, to verify the effectiveness of the improved DBC, the simulation results are provided in comparison to the conventional DBC.

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High Speed Photonic Time-Stretched ADC based on Dispersion-Tunable CFBG 20

High Speed Photonic Time-Stretched ADC based on Dispersion-T...

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20th International Conference on Optical Communications and Networks, ICOCN 2022

作者： Li, Shangru Xiao, Dongrui Liu, Shuaiqi Yu, Feihong Xu, Weijie Hu, Jie Sun, Siming Shao, Liyang Zhang, Qingfeng Southern University of Science and Technology Department of Electrical and Electronic Engineering Shenzhen518055 China State Key Laboratory of Analog and Mixed-Signal VLSI University of Macau 999078 China Peng Cheng Laboratory Shenzhen518005 China

A single-channel PTS-ADC based on dispersion-Tunable CFBG is proposed to realize tunable sampling rate. Seven different sampling rates corresponding to different stretching factors are obtained. The total sampling rat... 详细信息

ISBN: (数字)9781665458986

ISBN: (纸本)9781665458986

关键词： Fiber Bragg gratings

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An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4thNyquist Zone in 1GS/s ADC 35

An Auxiliary-Channel-Sharing Background Distortion and Gain ...

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35th Symposium on vlsi Circuits, vlsi Circuits 2021

作者： Wei, Lai Zheng, Zihao Markulic, Nereo Lagos, Jorge Martens, Ewout Zhu, Yan Chan, Chi-Hang Craninckx, Jan Martins, Rui Paulo University of Macau State-Key Laboratory of Analog and Mixed Signal Vlsi Ime DECE/FST China Imec Leuven Belgium

ISBN: (纸本)9784863487796

This paper presents an auxiliary-channel-assisted background calibration for ADC's input front-end (buffer + T/H) distortion and inter-stage gain error. The auxiliary channel is custom-designed which runs at a fractional speed of the main ADC with only moderate noise performance but high linearity. It also has a pseudo inter-stage gain characteristic as the main ADC, which incorporates with the multi-layer LMS procedure, facilitating a fast convergence speed. Verified in a 12-bit 1GS/s pipelined SAR ADC in 28nm CMOS, the SNDR and SFDR at Nyquist input are 59.28 dB and 67.09 dB SFDR, respectively. Just the distortion calibrations alone contribute >11.13dB SFDR improvement in the entire Nyquist band. Both the ADCs and input buffers work under a 1V supply, consuming 19.2mW with 17% from the buffer. © 2021 JSAP.

关键词： Calibration

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A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and analog Non-Uniform Quantization

A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial ...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Guoqiang Xin Fei Tan Junde Li Junren Chen Wei-Han Yu Ka-Fai Un Rui P. Martins Pui-In Mak The State-Key Laboratory of Analog and Mixed-Signal VLSI/IME and FST-ECE University of Macau Macao China on-leave from the Instituto Superior Técnico UL Portugal

ISBN: (数字)9798350387179

ISBN: (纸本)9798350387186

analog computing-in-memory (CIM) macro has been widely used in various machine learning (ML) applications, which parallelly perform energy- and area-efficient matrix-vector multiplication (MVM) operations. Compared with digital CIM, analog CIM has shown great efficiency on multi-bit MVM computations. However, the analog approaches accumulate the MVM results on the voltage domain, different accumulation lengths and data sparsity cause distinct signal swing degradation and variation. Hence, the analog-to-digital converter (ADC) readout circuit requires more power and area to trade off with the noise and comparator offset. In this paper, we proposed a partial sum boosting (PSB) method to give $4.6\times$ to $22.8\times$ signal swing enhancement for multi-bit MVM, which mitigates severe ADC overhead for analog CIM. Furthermore, multi-bit 5T-SRAMs with diverse voltage supplies realize multi-bit uniform/non-uniform sign-and-magnitude (SNM) weight representation and save up to $38.8\times$ SRAMs static power dissipation. The chip was fabricated in 28nm CMOS technology and measured a throughput density of 89.04 TOPS $/\text{mm}^analog$ and energy efficiency of 219.5 TOPSIW under 3-bit activation, 4-bit SNM weight with no truncation 5-bit partial sum readout condition.

关键词： Weight measurement Semiconductor device measurement Quantization (signal) Density measurement Energy measurement In-memory computing Boosting

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Preliminary Research on Super-Regenerative Receiver for Intracardiac Communication

Preliminary Research on Super-Regenerative Receiver for Intr...

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2023 Cross Strait Radio Science and Wireless Technology Conference, CSRSWTC 2023

作者： Weng, Xueyu Li, Dongming Zhao, Wenxiang Pun, Sio Hang Vai, Mang I. Gao, Yueming College of Advanced Manufacturing Fuzhou University China Fuzhou University The International Joint Laboratory on Health Intelligent Monitoring Systems China University of Macau State Key Laboratory of Analog and Mixed-Signal VLSI China University of Macau Faculty of Science and Technology China College of Physics and Information Engineering Fuzhou University China

ISBN: (纸本)9798350358971

Existing commercial pacemakers only provide single-chamber pacing and cannot achieve multi-chamber sequential pacing. Conduction Intracardiac Communication(CIC) has the characteristics of low power consumption and high security, which is very suitable for communication between multi-chamber leadless pacemakers. Because the pacemaker needs to be implanted into the heart, which limits its volume, power consumption, and other related parameters, and the super-regenerative circuit has its low power consumption and simple circuit structure, the super-regenerative receiver scheme is a good choice for intracardial communication where power consumption is the main problem. In this paper, a prototype super-regenerative receiver suitable for intracardiac communication is proposed. The differential instrument amplifier with high input impedance is used to filter out the external electromagnetic interference, reduce the input equivalent noise, and improve the signal-to-noise ratio. A super-regenerative oscillator and a filter amplifier circuit are designed to enhance the effectiveness and reliability of the communication. The experimental results show that the bit error rate of the circuit is lower than 1 × 10-5 for the received signal of -92 dBm. © 2023 IEEE.

关键词： CIC Leadless pacemaker super-regenerative

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A LDO with 5-nA Quiescent Current and Improved Transient Response within a 50-mA Load Current Range

A LDO with 5-nA Quiescent Current and Improved Transient Res...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Zaitian Yang Qiujin Chen Shaowei Zhen Mo Huang State Key Laboratory of Analog and Mixed-Signal VLSI University of Macau Macao China School of Integrated Circuit Science and Engineering University of Electronic Science and Technology of China Chengdu China

ISBN: (数字)9798350330991

ISBN: (纸本)9798350331004

A Low-Dropout Regulator (LDO) with low quiescent current is proposed. The LDO uses a variable capacitance tracking zero compensation to enhance the stability within a wide load current range. Furthermore, it utilizes adaptive biasing current for a low quiescent current at the steady-state, while a transient enhancement circuit to improve transient response. Designed with a 65-nm CMOS process, the proposed LDO consumes a 5-nA quiescent current and supports a maximum 50-mA load current. The simulated output undershoot is 137 mV when the LDO has a load current step from 0 to 50 mA, with a 0.4-ns edge time.

关键词： Transient response Regulators Circuits and systems Capacitance CMOS process Stability analysis Circuit stability

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