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Dual Multimodal Fusions with Convolution and Transformer Layers for VLSI Congestion Prediction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems 2024年第6期44卷 2378-2391页

作者： Gu, Hao Wang, Youwen Zheng, Xinglin Peng, keyu Zhu, Ziran Chen, Jianli Yang, Jun The National ASIC System Engineering Research Center School of Integrated Circuits Southeast University Nanjing210096 China The State Key Lab of ASIC & System Fudan University Shanghai200433 China

In very large scale integration (VLSI) circuit physical design, precise congestion prediction during placement is crucial for enhancing routability and accelerating design processes. Existing congestion prediction models often encounter challenges in handling multimodal information and lack effective fusion of placement and netlist features, limiting their prediction accuracy. In this paper, we present a novel congestion prediction model that leverages dual multimodal fusions with convolution and transformer layers to effectively capture the multiscale placement information and enhance congestion prediction accuracy. We first adopt convolutional neural networks (CNN) to extract grid-based placement features and heterogeneous graph convolutional networks (HGCN) to extract netlist information. To help the model understand the correlation between different modalities, we then propose an early feature fusion (EFF) to integrate netlist knowledge into multiscale placement features at multimodal interaction subspace. Besides, a deep feature fusion (DFF) method is proposed to further fuse multimodal features, which has multiple vision transformer layers based on adaptive attention enhancement technology. These layers include self-attention to boost intra-modal features and cross-attention to perform cross-modal feature fusion on netlist and grid-based placement features. Finally, the output features of DFF are sent into the cascaded decoder to recover the congestion map by exploiting several upsampling layers and merging with EFF features. Compared with the existing state-of-the-art congestion prediction models, experimental results demonstrate that our model not only outperforms them in prediction accuracy, but also excels in reducing routing congestion when integrated into the placer DREAMPlace. © 1982-2012 IEEE.

关键词： VLSI circuits

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SDAcc: A Stable Diffusion Accelerator on FPGA via Software-Hardware Co-Design 32

SDAcc: A Stable Diffusion Accelerator on FPGA via Software-H...

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32nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2024

作者： Zhou, Hao Liu, Yang Wang, Hongji Tang, Enhao Li, Shun Zhang, Yifan Wang, Kun State Key Lab of ASIC & System Fudan University Shanghai China

ISBN: (纸本)9798350372434

Stable Diffusion has become one of the mainstream image synthesis algorithms. The mainstream computing platform for Stable Diffusion is GPU. However, the deployment of Stable Diffusion on GPU still faces the problems of power consumption. With dedicated hardware design and optimization, FPGA based Stable Diffusion accelerator can achieve better performance of energy efficiency. In this paper, we propose SDAcc for realizing efficient inference of Stable Diffusion on FPGA. SDAcc is 4.40× faster than CPU. Compared to GPU and CPU, SDAcc achieves 1.27× and 19.66× energy efficiency improvement, respectively. © 2024 IEEE.

关键词： Computer graphics equipment

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2D Ruddlesden-Popper Perovskites/PVDF-TrFE Photodetector for Anti-Interference Vision system Derived from Ferroelectric Polarization Modulation

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ADVANCED FUNCTIONAL MATERIALS 2025年第20期35卷

作者： Zhang, Xinglong Hong, Enliu Tan, Xiaojun Liu, Jie Jiang, Anquan Fang, Xiaosheng Fudan Univ Dept Mat Sci State Key Lab Mol Engn Polymers Shanghai 200433 Peoples R China Shaoxin Lab Shaoxing 312000 Peoples R China Fudan Univ Sch Microelect State Key Lab ASIC&System Shanghai 200433 Peoples R China

2D Ruddlesden-Popper (RP) perovskites have garnered increasing attention for their excellent photoresponse, characterized by high carrier mobility, tunable bandgaps, high optical absorption, and molecular asymmetry. Herein, centimeter scale single crystal 2D hybrid perovskites, BA2PbBr4 (BPB) is synthesized, using quasi-static cooling method and composited with ferroelectric PVDF-TrFE(PT) film to construct a multi-field coupling photodetector (PD) via van der Waals force contact. Ferroelectric tests show that the PT film exhibits a saturated polarization strength of 3.6 mu C cm-2, allowing the ferroelectric localized field to modulate the band structure of PT and enhance the photocurrent. The Heterojunction systems exhibit ultra-high responsivity (15.3 A W-1) and detectivity (1.99 x 1013 Jones) under 390 nm illumination at 3 V bias, with a performance improvement of over 102 times compared to BPB PDs. Furthermore, the hybrid PDs exhibit highly stable I-t curve with a photocurrent retention rate of 97.4%. Leveraging this feature, a large-area imaging device is designed at the centimeter level scale, enabling multifunctional vision applications accurate letter imaging process and anti-interference number detection. The work presents a valuable insight in design of future autonomous driving vision systems.

关键词： 2D Ruddlesden-Popper perovskites ferroelectric photodetector PVDF-TrFE single-crystal

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Design memristor-based computing-in-memory for AI accelerators considering the interplay between devices, circuits, and system

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Science China(Information Sciences) 2023年第8期66卷 243-253页

作者： Junjie AN Linfang WANG Wang YE Weizeng LI Hanghang GAO Zhi LI Zhidao ZHOU Jinghui TIAN Jianfeng GAO Chunmeng DOU Qi LIU School of Microelectronics University of Science and Technology of China State key Lab of Fabrication Technologies for Integrated Circuits Institute of MicroelectronicsChinese Academy of Sciences School of Microelectronics University of Chinese Academy of Sciences Frontier Institute of Chip and System State Key Laboratory of ASIC and System Fudan University

Recent advances in developing beyond von Neumann architectures have moved the memristive devices to the forefront as one of the key enablers to realizing memristive computing-in-memory(m CIM)structures, which shows a great promise to boost the energy-efficiency and the performance of artificial intelligence(AI) chips. In this study, by considering the interactions between devices, circuits, and systems in the m CIM design, we propose several cross-layer design techniques, including(1) the BL-SL interactive forming protection(BSIFP) circuit that can reduce the voltage drop on the selected transistor, suppress the current overshoot by 65.96%, and improve the bit-cell density by more than 10.19%,(2) the clamping transistor trimming scheme(CTTS) to prevent the multiply-and-accumulate(MAC) signal margin degradation from chip-to-chip resistance variations, and(3) dynamic input-parallelism and output-precision(DIPOP) that can reduce the energy cost by 22.92% in a typical inference task with negligible accuracy loss. The results demonstrate the significant role of the cross-layer-interactive approach and provide a preliminary guideline for highly-efficient m CIM design.

关键词： memristor resistive memory computing-in-memory artificial intelligence cross-layer co-design

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A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology 15

A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm ...

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15th IEEE International Conference on asic, asicON 2023

作者： Lyu, Bingrong Ye, Fan Ren, Junyan Fudan University State Key Lab. of ASIC & System Shanghai China

ISBN: (纸本)9798350312980

A 6-Gb/s half rate current mode logic (CML) transmitter has been designed in TSMC 28nm CMOS technology, which employs a 3-tap 3-bit feed forward equalizer (FFE), an analog duty cycle correction module (DCC) for half rate clock and a 5-bit output impedance calibration module for 100-ohm differential load. Post-layout simulation indicates that the FFE could compensate for up to 4.7dB channel loss at 3GHz while maintaining 410mVpp eye height. The DCC module could corrects±30% duty cycle mismatch and max deviation of the calibrated impedance is 2.7%. Implemented in 28nm CMOS technology, the transmitter delivers 6-Gb/s data (215-1 PRBS) with 4.7dB channel attenuation at 3GHz. The transmitter (excluding clock generating PLL) consumes 27.67mA from 0.9V supply and occupies a die area of 214μm ∗ 108μm. © 2023 IEEE.

关键词： CML driver duty cycle correction impedance calibration wireline transmitter

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A Decision-Based CORDIC Hardware for Arc Tangent Calculation 15

A Decision-Based CORDIC Hardware for Arc Tangent Calculation

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15th IEEE International Conference on asic, asicON 2023

作者： Wu, Haoyu Lin, Liyu Sun, Haodong Zeng, Xiaoyang Chen, Yun Fudan University State Key Lab of ASIC & System Shanghai200433 China

ISBN: (纸本)9798350312980

The COordinate Rotation DIgital Computer (CORDIC) simplifies the elementary function using bit-shift operation and addition. However, the iteration increases with the accuracy and causes a long latency. In this paper, we propose a decision-based CORDIC hardware for arc tangent calculation, which introduce a comparator to determine the necessity of the rotation in every iteration. By bypassing the redundant processes, the proposed CORDIC achieve a higher accuracy. Besides, the regular structure is also friendly for folding implementation. Experiments show that compare with the conventional CORDIC, the decision-based CORDIC hardware has an improvement of 28.1% in accuracy. Synthesis results in 65nm technology shows that the proposed unfolding hardware consumes an area of 0.774mm2 and a power of 0.644mW under 65nm technology, which has an improvement of about 13.7% and 3% in comparison with the conventional CORDIC, and the folding structure has an area of 0.164mm2 and a power of 0.243mW. © 2023 IEEE.

关键词： arc tangent CORDIC Decision-Based

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Construction of mesoporous silica-implanted tungsten oxides for selective acetone gas sensing

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Chinese Chemical Letters 2024年第11期35卷 492-498页

作者： Jichun Li Zhengren Wang Yu Deng Hongxiu Yu Yonghui Deng Xiaowei Cheng Kaiping Yuan Department of Chemistry Shanghai Stomatological Hospital&School of StomatologyState Key Laboratory of Molecular Engineering of PolymersShanghai Key Laboratory of Molecular Catalysis and Innovative MaterialsiCHEMFudan UniversityShanghai 200433China Frontier Institute of Chip and System State Key Laboratory of ASIC and SystemFudan UniversityShanghai 200433China State Key Lab of Transducer Technology Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Shanghai 200050China

As a key biomarker for noninvasive diagnosis of diabetes,the selective detection of trace acetone in exhaled gas using a portable and low-cost device remains a great *** metal oxide(SMO)based gas sensors have drawn signification attention due to their potential in miniaturization,user-friendliness,high cost-effectiveness and selective real-time detection for noninvasive clinical ***,we propose a one-pot solvent evaporation induced tricomponent co-assembly strategy to design a novel ordered mesoporous SMO of silica-implanted WO_(3)(Si O_(2)/WO_(3))as sensing materials for trace acetone *** controlled co-assembly of silicon and tungsten precursors and amphiphilic diblock copolymer poly(ethylene oxide)-block-polystyrene(PEO-b-PS),and the subsequent thermal treatment enable the local lattice disorder of WO_(3)induced by the amorphous silica and the formation of ordered mesoporous Si O_(2)/WO_(3)hybrid walls with a unique metastableε-phase WO_(3)*** obtained mesoporous SiO_(2)/WO_(3)composites possess highly crystalline framework with large uniform pore size(12.0-13.3 nm),high surface area(99-113 m^(2)/g)and pore volume(0.17-0.23 cm^(3)/g).Typically,the asfabricated gas sensor based on mesoporous 2.5%Si O_(2)/WO_(3)exhibits rapid response/recovery rate(5/17 s),superior sensitivity(R_(air)/R_(gas)=105 for 50 ppm acetone),as well as high selectivity towards *** limit of detection is as low as 0.25 ppm,which is considerably lower than the thresh value of acetone concentration(>1.1 ppm)in the exhaled breath of diabetic patients,demonstrating its great prospect in real-time monitoring in diabetes ***,the mesoporous 2.5%Si O_(2)/WO_(3)sensor is integrated into a wireless sensing module connected to a smart phone,providing a convenient real-time detection of acetone.

关键词： Mesoporous materials ε-Tungsten oxide Silica-implanted Acetone sensing Real-time detection

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LTRNet: A Lightweight Topography Recognition Network 16

LTRNet: A Lightweight Topography Recognition Network

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Liu, Yixuan Song, Tianhui Chen, Yun Fudan University The State Key Lab of Asic & System Shanghai China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Topography recognition is essential for environmental science and ecological research. Conventionally, the deep-learning-based method will improve the recognition accuracy, but the large model size limits the application on the platform like UAVs (unmanned aerial vehicles). This paper proposes the LTRNet (Lightweight Topography Recognition Network) to improve accuracy and reduce computational complexity. Besides, we manually prepared a dataset located in China. 1545 DEM (digital elevation model) imagines are collected, including four categories of topography: city, hill, mountain, and plain. Experimental results on our dataset show that the LTRNet has an accuracy of 88.4% and only has a size of 0.58MB. © 2022 IEEE.

关键词： Topography

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A 3GHz Phase-Locked Loop Design for SerDes Application 16

A 3GHz Phase-Locked Loop Design for SerDes Application

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16th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2022

作者： Yang, Yuting Lyu, Bingrong Ye, Fan Ren, Junyan Fudan University State Key Lab. of Asic & System Shanghai China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

A 0.9V high performance 3GHz charge pump phase-locked loop (CP PLL) has been designed in TSMC 28nm CMOS technology, which features high accuracy charge pump (CP) and low phase noise LC voltage-controlled oscillator (LC-VCO). The nonideal effects and corresponding solutions for CP and LC-VCO are discussed in the paper. The post-layout simulation results show that the PLL could achieve 0.86ps rms jitter and 13mW power consumption at 3GHz. © 2022 IEEE.

关键词： Phase locked loops

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Conditional Cycle Termination RANSAC 17

Conditional Cycle Termination RANSAC

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17th IEEE International Conference on Solid-state and Integrated Circuit Technology, ICSICT 2024

作者： Jiang, Tong Huang, Yujie Peng, Liyuan Wang, Mingyu Li, Wenhong Jing, Minge Zeng, Xiaoyang Fudan University State Key Lab of ASIC & System Shanghai201203 China Shanghai ExploreX Technology Co. Ltd. Shanghai200120 China

ISBN: (纸本)9798350361834

In the field of computer vision, the acquired dataset usually contains a certain number of outliers and noise, which leads to errors in the estimated mathematical model. RANSAC estimates model parameters by randomly selecting a subset of the data, reducing the impact of these outliers and noise. However, for datasets with a high proportion of inliers, the traditional RANSAC has to perform a large number of cyclic modeling operations after finding the correct model. In this paper, a conditional termination verification strategy for RANSAC is presented. We boldly terminated the cycle operation early which reduced the amount of computation by 17.78% and increased the computation speed by 34.09%. © 2024 IEEE.

关键词： Conditional termination Inliers Model evaluation Outliers RANSAC

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