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Partitioned branch condition resolution logic 13

Partitioned branch condition resolution logic

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13th Symposium on Integrated Circuits and Systems Design

作者： Farooqui, A Current, KW Oklobdzija, VG Synopsys Inc Synopsys Module Compiler Grp Mountain View CA 94043 USA

ISBN: (纸本)076950843X

This paper presents the design of an early condition resolution circuit. The proposed circuit works in parallel with the arithmetic unit, and calculates the Equal to (EQ), Greater-than (GT), Less-than (LT), Overflow (OV), Underflow (UF), and Carry-out (C-out), conditions. The proposed logic is reconfigurable, and can calculate all the conditions (mentioned above) for one 64-bit, two 32-bit, four 16-bit, or eight 8-bit signed and unsigned operands. The reconfigurability of the logic is achieved using only four control signals. Two of the control signals (Part0, Part1) are used to partition the logic into 64, 32, 16, or 8-bit independent condition resolvers and the Sign control signal is used to control the signed/unsigned operation. The Add-Sub control signal specifies and controls the Add/Subtract operation for the condition resolution. In order to achieve high speed with reconfigurability and minimum area, new techniques are developed for calculating the conditions before the results are available. The proposed logic is designed for VLIW or Media processors, which require a high degree of reconfigurability, and high speed operation. It can also be used in MIPS family of processors for early branch condition resolution, to avoid branch stalls. Simulations of realizations in a standard digital CMOS fabrication technology show a 30% improvement in speed and a 25% savings in area using the approaches presented here.

关键词： Arithmetic CMOS logic circuits CMOS technology Delay Logic design Performance evaluation Reconfigurable logic Signal resolution Systems engineering and theory VLIW

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A programmable data-path for MPEG-4 and natural hybrid video coding

A programmable data-path for MPEG-4 and natural hybrid video...

引用

34th Asilomar Conference on Signals, Systems, and Computers

作者： Farooqui, AA Oklobdzija, VG Synopsys Module Compiler Grp Mountain View CA 94043 USA

ISBN: (纸本)0780365143

A programmable data-path that supports MPEG standards Synthetic & Natural Hybrid video Coding (SNHC) is presented. It can support a maximum of 16 parallel SIMD integer operations and 2 parallel SIMD floating-point operations. Two new instructions were added in order to increase the execution of 3D graphics and SNHC as well as to speed up IDCT, FFT, and other media signal processing algorithms. These operations are implemented by re-using the hardware without significant increase in area and delay. The datapath has been modeled in Verilog using 0.25u CMOS library and synthesized using synopsys. All operations are single-cycle running at 200 MHz.

关键词： Image coding

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Impact of architecture extensions for media signal processing on data-path organization

Impact of architecture extensions for media signal processin...

引用

34th Asilomar Conference on Signals, Systems, and Computers

作者： Farooqui, AA Oklobdzija, VG Synopsys Module Compiler Grp Mt View CA 94043 USA

ISBN: (纸本)0780365143

Media signal processing requires high completing power and the algorithms exhibit a great deal of parallelism on low precision data. The basic components of multi-media objects are usually simple integers with 8, 12, or 16 bits of precision, In order to support efficient processing of media signals, Instructions Set Architecture (ISA) of the traditional processors requires modifications. In this paper, we present the quantitative analysis and the computational complexity required to perform media processing. Main classes of instructions that are needed for the required level of performance of the Media Processor are identified Their efficient implementation and effect on the processor datapath is discussed. The main operations required in media processing are Addition (with or without saturation), Multiplication (with or without rounding), Sum of Products, and Average of two numbers.

关键词： Signal processing

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