We developed a multimodal sensor for proton (pH, power of Hydrogen) and filter-less fluorescence imaging by using CMOS (complementary metal-oxide semiconductor) silicon integrated circuittechnology. In the developed ...
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Modern FPGAs, such as the Xilinx Virtex-II Series, offer the feature of partial and dynamic reconfiguration, allowing to load various hardware configurations (i.e., HW modules) during run-time. To enable communication...
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An ultra-broadband analog correlator consisting of a four-quadrant multiplier and an ultra-fast resettable integrator using only NPN transistors was designed, fabricated, and measured. For the integrator, a cross-coup...
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The design of resource efficient integrated circuits (IC) requires solving a minimization problem of more than one objective given as measures of available resources. This multiobjective optimization problem (MOP) can...
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The increasing logic density of current FPGAs (Field Programmable Gate Arrays) enables the integration of whole systems on one programmable chip. Some of these FPGAs provide the additional feature of partial dynamic r...
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ISBN:
(纸本)0769521320
The increasing logic density of current FPGAs (Field Programmable Gate Arrays) enables the integration of whole systems on one programmable chip. Some of these FPGAs provide the additional feature of partial dynamic reconfiguration, which permits to change parts of the device while other parts keep working. Combining the features of system level density and partial dynamic re-configuration enables the integration of dynamic systems that can be adopted to changing demands during runtime. A lot of theoretical work in this challenging research area has been done on efficiently placing and scheduling modules on the FPGA area. However, there is a lack of applied approaches that can be realized by existing tools and FPGAs. In this paper we present a new, realizable approach for the dynamic system integration on Xilinx Virtex FPGAs. In contrast to the existing approaches that consider fixed slots for the module placement, our approach enables the fine-grained placement of modules with variable width along a horizontal communication infrastructure1.
Using radial basis function networks for function approximation tasks suffers from unavailable knowledge about an adequate network size. In this work, a measuring technique is proposed which can control the model comp...
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ISBN:
(纸本)2930307099
Using radial basis function networks for function approximation tasks suffers from unavailable knowledge about an adequate network size. In this work, a measuring technique is proposed which can control the model complexity and is based on the correlation coefficient between two basis functions. Simulation results show good performance and, therefore, this technique can be integrated in the RBF training procedure.
In this demo we show an ultra-low phase noise optoelectronic PLL (OEPLL) based on optical clock source. The output signal of this type of PLL is in the electrical domain and its reference oscillator, typically a mode-...
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In this paper we present the RAPTOR family as an advanced modular platform for both FPGA-based rapid prototyping and hardware acceleration. Using modern FPGAs and high speed communication links, performance and flexib...
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This paper describes the architecture and development of an innovative memory controller for the PowerPC family. HiBRIC-MEM (High Bandwidth Resource Interface Controller) provides control for up to two PowerPC process...
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ISBN:
(纸本)0818681306
This paper describes the architecture and development of an innovative memory controller for the PowerPC family. HiBRIC-MEM (High Bandwidth Resource Interface Controller) provides control for up to two PowerPC processors. A look-ahead mechanism, called stream cache, is used to reduce the effective memory latency and a 12-bit error correction code is available for optimal system security. Initial silicon was produced in a 0.7 mu m, three metal layer Motorola technology and has a die size of 12.1 x 12.1 mm(2). HiBRIC-MEM is used e.g. in a commercially available parallel computer.
The paper presents a new approach towards large system design in distributed teams based on a workflow technology. The techniques applied introduce interoperability among design tools across computing platforms and or...
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