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Appointments for 2005-2006 term

IEEE Transactions on Very Large Scale Integration (VLSI) systems 2005年第7期13卷 773-782页

作者： Ranganathan, Nagarajan Agrawal, Vishwani D. Chakradhar, Srimat T. Chakrabarty, Krishnendu Courtois, Bernard DeMara, Ronald Hu, Xiaobo Sharon Ismail, Yehea I. Jha, Niraj K. John, Lizy Kurian Ker, Ming-Dou Koren, Israel Liu, Bin-Da Marculescu, Diana Marculescu, Radu Narayanan, Vijaykrishnan Nassif, Sani R. Nowick, Steven M. Sapatnekar, Sachin S. Sherlekar, Sunil Sylvester, Dennis Vemuri, Ranga Pham, Michael Department of Computer Science and Engineering University of South Florida Tampa FL 33620 United States Department of Computer Science and Engineering Nanomaterials and Nanomanufacturing Research Center University of South Florida Tampa United States IEEE United States Systems United States Department of Electrical and Computer Engineering Rutgers University New Brunswick NJ United States IETE India ACM NEC Laboratories America Inc. Princeton NJ United States Duke University Durham NC United States ACM SIGDA Sigma Xi United States Laboratory of Techniques of Informatics and Microelectronics for Computer Architectecture ASME IMAPS IEEE Computer Society University of Central Florida Orlando United States Computer Engineering Program SEECS Department of Computer Science and Engineering University of Notre Dame Notre Dame IN United States Northwestern University Evanston IL United States Department of Electrical Engineering Princeton University Princeton NJ United States Association for Computing Machinery Austin United States UT Austin Engineering Foundation United States Department of Electronics Engineering National Chiao-Tung University Taiwan Department of Electrical and Computer Engineering University of Massachusetts Amherst United States Department of Electrical Engineering Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA United States Electrical and Computer Engineering Faculty Carnegie Mellon University Pittsburgh PA United States Computer Science and Engineering Department Pennsylvania State University University Park United States IBM Austin Research Laboratory Austin TX United States Columbia University New York NY United States Department of Electrical and Computer Engineering University of Minnesota Minneapolis United States Tata Consultancy Services Centre of Excellence for Embedded Systems India Department of Electrical Engineering IIT Bombay India Department of Electrical Engineering Uni

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Energy diffusion model of bR for voxel identification

Energy diffusion model of bR for voxel identification

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： D. Garcia Neto H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory-Department of Electrical and Systems Engineering Oakland University Rochester USA

In this paper, a potential biological structure for computer volumetric memory is investigated. Bacteriorhodopsin is a protein found in the purple membrane of the bacteria Halobacterium salinarum. This protein has light absorption properties that generate different stable states allowing the use of multilevel logic as well as binary logic. CHARMmtrade has been used to simulate the energy response of Bacteriorhodopsin at room temperature 300K for the bR ground state and the other states. The K state takes place after blue light (lambda= 635nm) absorption on the bR state. The energy difference is found to be an increase of 1086.92 kcal/mol which is responsible for triggering the photocycle that also includes the states K, L, M, N, and O. An energy surplus is found between O and bR state that may be spread to surrounding molecules. However, conformational interference does not produce photons necessary for the isomerization reaction. Further quantum molecular (QM) analysis should provide an extended model for this macromolecular energy study

关键词： Biological system modeling Proteins Absorption Logic Biology computing Biomembranes Microorganisms Computational modeling Land surface temperature Stationary state

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Equalizing data-path for processing speed determination in block level pipelining

Equalizing data-path for processing speed determination in b...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Xiaoyao Liang A. Athalye Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

Signal processing algorithms represented by data flow graphs can be efficiently mapped to hardware using a block level pipelining architecture. In this scheme, nodes of data flow are mapped to processing blocks and buffers are inserted in between as pipelining elements. We present, in this paper, a methodology for equalizing execution times of various nodes in the data path. The method is used to minimize the power dissipation and buffer usage by judiciously selecting the execution speed of hardware units. The block level pipelining allows for simple local controllers for each buffer which are generated by the global controller based on data flow specifications. The evaluation of the methodology on a practical example is presented.

关键词： Pipeline processing Communication system control Signal processing algorithms Control systems Hardware Centralized control Frequency synchronization Distributed control Mobile computing Laboratories

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Dynamic coarse grain dataflow reconfiguration technique for real-time systems design

Dynamic coarse grain dataflow reconfiguration technique for ...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Xiaoyao Liang A. Athalye Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

The paper explores a reconfigurable platform design methodology for high throughput execution of data centric applications. The reconfiguration platform consists of heterogenous processing elements and buffers interacting through reconfigurable interconnects. The proposed platform is based on block level pipelining with the buffers and their respective controllers forming the pipelining elements. We discuss the dynamic and partial reconfiguration techniques of this platform. Specifically, reconfiguration overhead at runtime is illustrated.

关键词： Real time systems Switches Integrated circuit interconnections Computer architecture Pipeline processing Reconfigurable architectures design methodology Throughput Digital signal processing Parallel processing

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Minimization of secondary effects in SOI: a 32-bit ANT logic adder implementation

Minimization of secondary effects in SOI: a 32-bit ANT logic...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A. Wasson Dipti Sanghvi A. Nunez VLSI Systems Design and CAD (VSDCAD) Laboratory Department of Electrical Engineering and Computer Science (EECS) Syracuse University Syracuse NY USA

This paper presents a review of circuit design techniques related to silicon on insulator technology (SOI) CMOS circuits. The most important design considerations are parasitic bipolar effect, floating body effect and hysteric variation in the threshold voltage. These effects lead to the reduction of the noise margin and under serious circumstances may lead to a wrong output. Dynamic circuits are most vulnerable to these effects due to the presence of a soft node at the top of the pull down stack. We have studied the various existing techniques and have proposed a design modification which alleviates the floating body effect without compromising other parameters like speed and without penalizing the charge sharing present. The approach is based on adding an extra transistor which will minimize the floating body effect without worsening charge sharing. The effectiveness of our design technique is demonstrated through its implementation in a 32-bit ANT logic carry look ahead adder using BSIMSOI models. Results show that the performance of the modified circuit is reliable and minimizes the floating body effect without adversely affecting charge sharing

关键词： Minimization Silicon on insulator technology Adders CMOS logic circuits Circuit synthesis CMOS technology Threshold voltage Noise reduction Circuit noise Logic design

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Pre-layout parasitic estimation in interconnects

Pre-layout parasitic estimation in interconnects

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： S. Shah A. Nunez Department of Electrical Engineering and Computer Science (EECS) VLSI Systems Design and CAD (VSDCAD) Laboratory Syracuse University Syracuse NY USA

Interconnect lengths have become a dominant factor in the design of integrated circuits. The parasitics associated with the interconnects account for a significant part of signal delay. The estimation of interconnect lengths prior to placement helps in determining the delay early in the design phase. In this paper, a methodology to estimate the interconnect lengths prior to layout, is presented. The approach is heuristics based. Various layouts have been studied to observe typical placement and routing patterns. The methodology uses the gate level netlist and properties of the cells obtained from the standard cell libraries for the estimation. The results have been compared with the detailed routing wire lengths obtained after synthesis of the gate level netlist. Cadence Buildgates was used for syntheises and Cadence Encounter used for placement and routing of the circuits. The methodology presented is independent of the technology being used. However the wire lengths will vary with the use of different placement and routing tools

关键词： Integrated circuit interconnections Wire Delay estimation Routing Circuit synthesis Capacitance Libraries Optimization methods Pins Very large scale integration

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Lighting energy efficiency - Visibility effectivity correlation

Lighting energy efficiency - Visibility effectivity correlat...

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2005 ASEE Annual Conference and Exposition: The Changing Landscape of engineering and Technology Education in a Global World

作者： Abrams, Marvin C. Smith, R. Frank Lewin, Ian Melnyk, Jack Cal Poly Pomona Univ. United States Lighting Sciences Inc. United States Southern California Edison Corp. United States College of Engineering Photo-optical Lighting and Electrical Systems Laboratory Lighting Education Program Lighting Sciences Inc. Scottsdale AZ United States Design Engineering Services Department Southern California Edison Inc. United States

This paper describes an example of augmenting classroom lecture and experiments with an actual engineering job-related experience. The impetus is to fulfill a student's need to see how their academic education is relevant to industry practice. Students from the ECE department Courses Introduction to Illumination and Lighting Control/design were offered the opportunity to participate in an applied research project sponsored by the Southern California Edison ( SCE ) company which was performed at the Cal Poly Pomona University (CPP). The courses cited provide instruction on illumination parameters such as spatial and spectral distribution, total luminosity, power and energy consumption, dimming, and design application of light sources. The experiments are bench top models of calculation, design, construction, and measurements. Present curricula methodology involves a strong reliance on software simulation. Students and faculty often become so dominantly indoctrinated and highly skilled in this mode that it can compromise the relationship between the learning experience of appreciating and distinguishing the relationship between physical reality and validation of actual and simulated results. The SCE project involved the measurement of illumination intensity and data reduction from a student questionnaire. The questionnaire sought to determine if there was a correlation between the visual effectiveness of high pressure sodium (HPS) versus pulse-start, metal halide (PSMH) luminaires in the Cal Poly Pomona parking lots. The Cal Poly Pomona College of engineering maintains a strong interactive relationship with industry advisory and partner committees to help make the engineering program as relevant as possible for it 4,700 students. This type of academic course-industry project is encouraged for many upper division classes.

关键词： engineering education

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Transport of Mars-Crossing Asteroids from the Quasi-Hilda Region

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Physical Review Letters 2005年第23期94卷 231102-231102页

作者： Michael Dellnitz Oliver Junge Martin W. Lo Jerrold E. Marsden Kathrin Padberg Robert Preis Shane D. Ross Bianca Thiere Faculty of Computer Science Electrical Engineering and Mathematics University of Paderborn D-33095 Paderborn Germany Navigation and Mission Design Jet Propulsion Laboratory California Institute of Technology M/S 301-140L 4800 Oak Grove Drive Pasadena California 91109 USA Control and Dynamical Systems California Institute of Technology MC 107-81 Pasadena California 91125 USA Department of Aerospace and Mechanical Engineering University of Southern California Los Angeles California 90089 USA

We employ set oriented methods in combination with graph partitioning algorithms to identify key dynamical regions in the Sun-Jupiter-particle three-body system. Transport rates from a region near the 3∶2 Hilda resonance into the realm of orbits crossing Mars’ orbit are computed. In contrast to common numerical approaches, our technique does not depend on single long term simulations of the underlying model. Thus, our statistical results are particularly reliable since they are not affected by a dynamical behavior which is almost nonergodic (i.e., dominated by strongly almost invariant sets).

关键词： .graph orbits partitioning week ending Asteroids Preis Mars-Crossing Quasi-Hilda

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Toward multimodal human-robot cooperation and collaboration

Toward multimodal human-robot cooperation and collaboration

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Collection of Technical Papers - AIAA 1st Intelligent systems Technical Conference

作者： Perzanowski, Dennis Brock, Derek Bugajska, Magdalena Thomas, Scott Sofge, Donald Adams, William Skubic, Marjorie Blisard, Sam Cassimatis, Nicholas Trafton, J. Gregory Schultz, Alan C. Naval Research Laboratory Washington DC 20375 University of Missouri Columbia MO 65211 Rensselaer Polytechnic Institute Troy NY 12180 Intelligent Multimodal/Multimedia Systems Code 5512 Interface Design and Evaluation Code 5513 Intelligent Systems Code 5515 Electrical and Computer Engineering Department Department of Cognitive Science

ISBN: (纸本)156347719X

Our multimodal interface integrates speech recognition, natural language understanding, spatial reasoning and human cognitive models for completing specific tasks and for perspective-taking in locative oriented tasks. With natural language and gestures, we believe human-robot interaction and communication is facilitated. Instead of concentrating on the various modalities of the interface, users can concentrate on the task at hand. Likewise, by incorporating human cognitive models for handling spatial information and perspective-taking, as well as for specific task completion, a better match with the expectations that humans acquire from their human-human interactions should be obtained, further facilitating cooperation and collaboration in human-robot interactions.

关键词： Speech recognition

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Glitching power reduction through supply voltage adaptation mechanism for low power array structure design

Glitching power reduction through supply voltage adaptation ...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Sangjin Hong Shu-Shin Chin M. Sadasivam Mobile Systems Design Laboratory Department of Electrical and Computer Engineering Stony Brook University-SUNY Stony Brook NY USA

A novel supply voltage switching mechanism for reducing power dissipation of array structures is presented. With this mechanism, the supply voltage levels are successively activated by external clock signal in the direction of signal propagation. The mechanism eliminates power dissipated by the glitches while the speed of the array structure can be maintained. The mechanism is easily incorporated so that no circuit change in the existing array structure is required.

关键词： Power supplies Voltage Adaptive arrays Logic Switches Power dissipation Pipelines Registers Delay Clocks

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