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Fully equipped half bridge building block for fast prototyping of switching power converters

Fully equipped half bridge building block for fast prototypi...

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Annual IEEE Conference on Power Electronics Specialists (PESC)

作者： K. De Gusseme D.M. Van de Sype J. Van den Keybus A.P. Van den Bossche J.A. Melkebeek Electrical Energy Laboratory Ghent University Gent Belgium Electrical Energy Laboratory Department of Electrical Energy Systems and Automation Ghent University Ghent Belgium Department of Electrical Engineering Catholic University of Leuven Leuven-Heverlee Belgium

With the advent of high performance digital controllers, the time and effort to implement new control algorithms for the control of power electronic converters have decreased drastically. Nevertheless, the design and the practical implementation of power electronic converters, intended for testing new control algorithms, are still complicated and time consuming activities. Therefore, a fully equipped half bridge test platform was designed ready to use as a fundamental building block for various converter types. The test platform incorporates fault protection, measurements of well-selected voltages and currents, and is directly interfacable with most digital and analog controllers. Due to these features and the flexibility of the board, this half bridge converter can be used for research as well as for educational purposes in applications ranging from a simple 100 W buck converter up to 10 kW inverters for motor control. The platform is demonstrated in this paper by means of some basic converter topologies, the half bridge boost converter and the full bridge buck converter.

关键词： Prototypes Switching converters Bridge circuits Digital control Power electronics Buck converters Algorithm design and analysis Electronic equipment testing Protection Current measurement

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Petri net-based design of modular supervisors for remotely human control systems

Petri net-based design of modular supervisors for remotely h...

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SICE Annual Conference

作者： Jin-Shyan Lee Meng-Chu Zhou Pau-Lo Hsu Department of Electrical & Control Engineering National Chiao Tung University Hsinchu Taiwan Department of Electrical & Computer Engineering New Jersey Institute of Technology Newark NJ USA Laboratory of Complex Systems & Intelligence Science Institute of Automation Chinese Academy of Sciences Beijing China

ISBN: (纸本)4907764227

In an Internet-based control system, particular human operations may violate desired requirements and lead to destructive failure. For such human-in-the-loop systems, this paper extends the remote supervisory scheme by Lee and Hsu (2003) to a modular one so as to reduce the supervisor synthesis complexity. Also, remote human issued commands are guaranteed to meet required specifications. A rapid thermal process in semiconductor manufacturing systems is provided to show the practicability of the proposed approach.

关键词： Humans Control systems Supervisory control Automatic control Internet Control system synthesis Rapid thermal processing Error correction Control engineering Intelligent systems

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Unified, periodic & sampled data H/sub /spl infin// control using the delta operator

Unified, periodic & sampled data H/sub /spl infin// control ...

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IEEE Conference on Decision and Control

作者： B. Lennartson R. Middleton A.-K. Christiansson Control and Automation Laboratory Department of Signals and Systems Chalmers University of Technology Goteborg Sweden Complex Dynamic Systems & Control School of Electrical Engineering & Computer Science University of Newcastle Callaghan NSW Australia University of Trollhättan/Uddevalla Trollhattan Sweden

A unified and general framework is presented for H/sub /spl infin// control of mixed continuous-time and discrete-time time-varying (periodic) systems. Using the delta operator, a close relationship is shown between the continuous- and discrete-time solutions. No assumptions are made on certain system matrices being zero or normalized, which makes the approach general and easy to apply. A combined continuous/discrete-time lifting procedure is shown to be useful, especially for ill-conditioned systems. This procedure together with the delta formalism results in a numerically robust design method concerning both short and long sampling periods for systems with W-conditioned dynamics, including widely spread eigenvalues.

关键词： Control systems Sampling methods Riccati equations Automatic control Robustness design methodology Eigenvalues and eigenfunctions Differential equations automation Laboratories

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VLSI design of high-throughput processing element for real-time particle filtering

VLSI design of high-throughput processing element for real-t...

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International Symposium on Signals, Circuits and systems, SCS 2003

作者： Chin, Shu-Shin Hong, Sangjin Mobile Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York at Stony Brook Stony BrookNY11794-2350 United States

ISBN: (纸本)0780379799

This paper presents a VLSI ASIC design of a high-throughput processing element for real-time particle filtering applications. The implementation is based on robust and efficient fixed-point processing algorithms. The high-throughput is achieved through two-level pipelining and preserving the inherent parallelism. The pipeline depth is balanced among sub-units to reduce clock loading via reduction of unnecessary registers. The processing element can be used as a standalone particle filter or a part of parallel particle filters for high-speed and/or larger particles. © 2003 IEEE.

关键词： Monte Carlo methods

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A monolithic spectral BIST technique for control or test of analog or mixed-signal circuits

A monolithic spectral BIST technique for control or test of ...

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IEEE International Symposium on Defect and Fault Tolerance in VLSI systems

作者： J.M. Emmert J.A. Cheatham Badhri Jagannathan Sandeep Umarani Microelectronic Design Automation and Test Laboratory Department of Electrical Engineering Wright State University USA

Intelligent radio frequency (RF) front ends make use of MMIC and MEMS devices to provide a limited range of programmability to what have historically been fixed resistive, capacitive, and inductive impedance matching networks. Many BIST methods for mixed-signal systems can also be used to monitor and provide feedback for the control of such RF systems. For example, spectral techniques can be used to analyze and determine the center frequency of a bandpass filter. Information relative to the center frequency can then be fed back into the system, and adjustments can be made to fine tune the filter. In this paper, we outline our spectral based, mixed-signal approach for monitoring the health of analog and RF components in mixed-signal systems on-chip. In our approach we use well known DSP techniques based an the FFT for on-chip signal generation and analysis. We reduce required hardware by using the same functional block to analyze analog output signals that we use to generate m tone stimulus signals. By providing an on-chip functional test capability, we also reduce the test time required on expensive ATE. Our techniques have been prototyped and demonstrated on a Xilinx Virtex-II FPGA using an off-chip ADC and DAC, and we are currently implementing the technique on an ASIC using a 0.13 /spl mu/m process with target execution speeds of 2-16 GHz.

关键词： Circuit testing Built-in self-test Radio frequency Monitoring Band pass filters Signal generators Signal analysis Intelligent networks MMICs Microelectromechanical devices

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Collaborative QoS architecture between DiffServ and 802.11e Wireless LAN

Collaborative QoS architecture between DiffServ and 802.11e ...

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57th IEEE Semiannual Vehicular Technology Conference (VTC2003)

作者： Park, Seyong Kim, Kyungtae Kim, Doug C. Choi, Sunghyun Hong, Sangjin Mobile Systems Design Laboratory Department of Electrical Engineering Stt. Univ. New York at Stony Brook Stony Brook NY 11794-2350 United States Multimedia/Wireless Networking Lab. School of Electrical Engineering Seoul National University Seoul 151-744 Korea Republic of

As the multimedia applications such as Voice over IP (VoIP) and Audio/Visual (AV) streaming across the Internet emerge, many are working on the network architecture to extend such applications to the wireless networking domain. The emerging IEEE 802.11e Quality-of-Service (QoS)-enabled Wireless LAN (WLAN) is considered a strong candidate for the air interface for such multimedia applications thanks to the IP-centric network paradigm along with its inherent high-speed transmission capability. This paper provides an integrated wired/wireless network architecture interfacing QoS between user level traffic over IP using Differentiated Service (DiffServ) and transport level traffic using IEEE 802.11e WLAN. Our study investigates the correlations in end-to-end traffic management between DiffServ and 802.11e, and presents the hierarchical QoS signaling interface between DiffServ and 802.11e, in terms of traffic classifying, shaping and policing.

关键词： Mobile computing

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Dynamic scheduling issues in SMT architectures

Dynamic scheduling issues in SMT architectures

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Chulho Shin Seong-Won Lee J.-L. Gaudiot Samsung Electronics Corporation System Design Technology Laboratory Department of Electrical Engineering-Systems University of Southern California USA Department of Electrical Engineering and Computer Science University of California Irvine USA

Simultaneous multithreading (SMT) attempts to attain higher processor utilization by allowing instructions from multiple independent threads to coexist in a processor and compete for shared resources. Previous studies have shown, however, that its throughput may be limited by the number of threads. A reason is that a fixed thread scheduling policy cannot be optimal for the varying mixes of threads it may face in an SMT processor. Our adaptive dynamic thread scheduling (ADTS) was previously proposed to achieve higher utilization by allowing a detector thread to make use of wasted pipeline slots with nominal hardware and software costs. The detector thread adaptively switches between various fetch policies. Our previous study showed that a single fixed thread scheduling policy presents much room (some 30%) for improvement compared to an oracle-scheduled case. In this paper, we take a closer look at ADTS. We implemented the functional model of the ADTS and its software architecture to evaluate various heuristics for determining a better fetch policy for a next scheduling quantum. We report that performance could be improved by as much as 25%.

关键词： Dynamic scheduling Surface-mount technology Yarn Processor scheduling Detectors Multithreading Throughput Face detection Adaptive scheduling Pipelines

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Layout-aware analog system synthesis based on symbolic layout description and combined block parameter exploration, placement and global routing

Layout-aware analog system synthesis based on symbolic layou...

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IEEE Computer Society Annual Symposium on VLSI

作者： Hua Tang Hui Zhang A. Doboli VLSI Systems Design Laboratory Electrical and Computer Engineering Department State University of New York Stony Brook NY USA

ISBN: (纸本)0769519040

This paper presents a new methodology for layout-aware synthesis of analog systems. The methodology combines block parameter exploration, block placement and global interconnect routing while maintaining an accurate perspective on the layout parasitics. An original system representation (called Layout Constraint Graphs - LCG) was developed for synthesis. The paper discusses how block parameter exploration, placement and global routing are expressed in terms of the LCG graph. AC and transient performances of each explored solution are obtained using SPICE simulations. Experiments show the generality of the synthesis methodology by providing results for several applications including filters and converters.

关键词： Routing Signal synthesis Circuit synthesis design optimization Circuit simulation Wire Laboratories Integrated circuit interconnections SPICE design automation

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Application specific coarse-grained FPGA for processing element in real time parallel particle filters

Application specific coarse-grained FPGA for processing elem...

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IEEE International Workshop on System-on-Chip for Real-Time Applications

作者： M. Sadasivam Sanjing Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York Stony Brook Stony Brook NY USA

This paper presents an application specific reconfigurable architecture based on coarse-grain FPGA for real-time parallel particle filters. The architecture consists of a set of heterogeneous arithmetic units and buffer banks, where their interconnections are reconfigurable at the hardware level. The proposed architecture separates fixed and reconfigurable units for high-throughput realization. We compare potential throughput of the design with that of commercial FPGAs and DSPs. The proposed architecture is implemented in 0.25 /spl mu/m CMOS process.

关键词： Field programmable gate arrays Particle filters Computer architecture Throughput Digital signal processing Particle tracking Filtering Application software Reconfigurable architectures Real time systems

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Exploring the biocomputing frontier

Exploring the biocomputing frontier

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： R.L. Ewing H.S. Abdel-Aty-Zohdy L. Liou J.B. Moncrief Information Directorate US Air Force Research Laboratory OH USA Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

Stop thinking that the universe is best described by Boolean order operations, consider the world of biocomputing. The idea in exploring the multidimensional characteristics of biocomputing systems involves multilevel protein logic interaction with hybrid digital systems (bio/digital/analog systems). In the protein biocomputing world, all models are multilevel and nonlinear exponential in nature. These biocomputing systems are linearized by boundary limited frequency, time response and dimensional ranges. The protein model and its correct development is probably the most difficult aspect for biocomputing issues. Previous protein models were not dealing with 2 and 3 dimensional models, while the current protein models are now faced with high frequency design, due to the emergence of bio-nanodevices. These future biocomputing devices will be chemical sensors, fluidic computer systems, optical switches, nanoactuators, self-repairing polymorphic computing systems, cognitive processors and biorobotics

关键词： Frequency Optical computing Multidimensional systems Logic Digital systems Time factors Protein engineering Chemical sensors Optical switches Nanoscale devices

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