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Collaborative QoS architecture between DiffServ and 802.11e wireless LAN

Collaborative QoS architecture between DiffServ and 802.11e ...

引用

IEEE Conference on Vehicular Technology (VTC)

作者： Seyong Park Kyungtae Kim D.C. Kim Sunghyun Choi Sangjin Hong Mobile Systems Design Laboratory Department of Electrical and Computer Engineering State University of New York Stony Brook Stony Brook NY USA Multimedia & Wireless Networking Laboratory School of Electrical Engineering Seoul National University Seoul South Korea

As the multimedia applications such as voice over IP (VoIP) and audio/visual (AV) streaming across the Internet emerge, many are working on the network architecture to extend such applications to the wireless networking domain. The emerging IEEE 802.11e quality-of-service (QoS)-enabled wireless LAN (WLAN) is considered a strong candidate for the air interface for such multimedia applications thanks to the IP-centric network paradigm along with its inherent high-speed transmission capability. This paper provides an integrated wired/wireless network architecture interfacing QoS between user level traffic over IP using differentiated service (Diffserv) and transport level traffic using IEEE 802.11e WLAN. Our study investigates the correlations in end-to-end traffic management between Diffserv and 802.11e, and presents the hierarchical QoS signaling interface between Diffserv and 802.11e, in terms of traffic classifying, shaping and policing.

关键词： Collaboration Diffserv networks Wireless LAN Telecommunication traffic Streaming media Collaborative work Internet telephony IP networks Quality of service Wireless networks

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Analysis of IR-drop scaling with implications for deep submicron P/G network designs

Analysis of IR-drop scaling with implications for deep submi...

引用

IEEE International Symposium on Quality Electronic design

作者： A.H. Ajami K. Banerjee A. Mehrotra M. Pedram Magma Design Automation Cupertino CA USA Department of Electrical Engineering-Systems University of Southern California Los Angeles CA USA Electrical and Computer Engineering Department University of California슠Santa Barbara Santa Barbara CA USA Computer and System Research Laboratory University of Illinois Urbana-Champaign IL USA

This paper presents a detailed analysis of the power-supply voltage (IR) drop scaling in DSM technologies. For the first time, the effects of temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis. It is shown that the IR-drop effect in the power/ground (P/G) network increases rapidly with technology scaling, and using well-known counter measures such as wire-sizing and decoupling capacitor insertion with resource allocation schemes that are typically used in the present designs may not be sufficient to limit the voltage fluctuations over the power grid for future technologies. It is also shown that such voltage drops on power lines of switching devices in a clock network can introduce significant amount of skew which in turn degrades the signal integrity.

关键词： Voltage Land surface temperature Electromigration Conductivity Electrons Scattering Counting circuits Power measurement Switched capacitor networks Resource management

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Paradigm of design for biosystem-on-a-chip(BioSoC)

Paradigm of design for biosystem-on-a-chip(BioSoC)

引用

IEEE International Conference on Microelectronic systems Education

作者： R.L. Ewing H.S. Abdel-Aty-Zohdy Information Directorate Air Force Research Laboratory Air Force Institute of Technology Department of Electrical and Computer Engineering Wright Patterson Air Force Base OH USA Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

The paradigm of design for biosystem-on-a-chip (BioSoC), is that multidisciplinary skills are required. Thus, the educational goals are to develop an understanding of micro/macro collaboration along with the ability to apply and use multidisciplinary skills for the design and performance evaluation of a "biosystem on a chip". The need for the architectural design of the BioSoC addresses the next-generation of intelligent information processing systems.

关键词： Intelligent sensors Collaboration design engineering Biology computing Chemical and biological sensors Biosensors Artificial intelligence Microelectronics Circuits Chemical sensors

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Piecewise-linear modeling of analog circuits using trained feed-forward neural networks and adaptive clustering of hidden neurons

Piecewise-linear modeling of analog circuits using trained f...

引用

International Joint Conference on Neural Networks (IJCNN)

作者： S. Doboli G. Gothoskar A. Doboli Computer Science Department Hofstra University Hempstead NY USA VLSI Systems Design Laboratory Electrical and Computer Engineering Department SUNY Stony Brook Stony Brook NY USA

This paper presents a new technique for automatically creating analog circuit models. The method extracts piecewise linear models from trained neural networks. A model is a set of linear dependencies between circuit performances and design parameters. The paper illustrates the technique for an OTA circuit - an amplifier circuit widely used in filters and A/D converters for which models for gain and bandwidth were automatically generated. As experiments show, the obtained models have simple form that accurately fits the sampled points and the behavior of the trained neural networks. These models are useful for fast simulation of systems with non-linear behavior and performances.

关键词： Piecewise linear techniques Analog circuits Feedforward systems Neural networks Feedforward neural networks Adaptive systems Neurons Filters Bandwidth Circuit simulation

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Application of novel hierarchical approach to formal verification of digital ICs

Application of novel hierarchical approach to formal verific...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： F.A. El-Licy H.S. Abdel-Aty-Zohdy Department of Information and Computer Science Institute of Statistical Studies and Research Cairo University Egypt Microelectronics System Design Laboratory Electrical and Systems Engineering Oakland University MI USA

A hierarchical approach for the abstraction of digital VLSICs is presented. Circuit layout is hierarchically abstracted into logical constructs of binary tree structures, which may be manipulated to extract circuit functionality for the purpose of verifying design correctness. VLSIC design specification in the form of HDL is hierarchically decomposed to generate logical formulae for the given specification. By comparing the above, a verification report is obtained

关键词： Formal verification Logic design Binary trees Hardware design languages Production Very large scale integration electrical capacitance tomography Combinational circuits Data structures Boolean functions

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Employing layout-templates for synthesis of analog systems

Employing layout-templates for synthesis of analog systems

引用

2002 45th Midwest Symposium on Circuits and systems

作者： Tang, Hua Doboli, Alex VLSI Systems Design Laboratory Electrical Engineering Department Stt. Univ. New York Stony Brook Stony Brook NY 11794-2350 United States

This paper presents an original methodology for layout-aware synthesis of analog systems. Layout parasitics (including capacitance, resistance and inductance) have a critical influence on system performances i.e. speed, bandwidth etc. We discuss the usage of layout templates during an exploration-based synthesis methodology that performs combined system parameter search, floorplanning and global routing. Predefined templates express the relative position of block and wires so that routing parasitics can be fastly extracted and considered during synthesis. The paper also presents the selection of the best layout template from a set of possible candidates. Two case studies are presented to exemplify the usage of layout templates for synthesis.

关键词： Integrated circuit layout

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Low power VLSI architecture of Viterbi scorer for HMM-based isolated word recognition

引用

IEEE International Symposium on Quality Electronic design

作者： Bok-Gue Park Koon-shik Cho Jun-Dong Cho VLSI Algorithmic Design Automation Laboratory Department of Electrical and Computer Engineering SungKyunKwan University South Korea

ISBN: (纸本)0769515614

HMM-based algorithms have been successfully applied to speech recognition since HMM provides a robust modeling capability of various speech signals and maintains high recognition accuracy. Viterbi scoring that searches the best matching word by comparing input utterance with reference speech models is a major task in HMM-based speech recognition. However, due to its operation complexity, Viterbi scoring is a significant source of power and computation when it is implemented by a dedicated VLSI architecture. This paper proposes a noble low power VLSI architecture of Viterbi scorer using modified Viterbi scoring procedure and precomputing logic. This method reduced power consumption by 20% and 27% for 100 and 400 candidate word recognition, respectively, compared with a conventional architecture at a cost of at most 12% increase in area due to additional control logics. As the device shrinks, power consumption becomes more significant than chip area.

关键词： Very large scale integration Viterbi algorithm Hidden Markov models Speech recognition Computer architecture Low pass filters Robustness Automatic speech recognition Logic devices Energy consumption

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Analog multiplexing in time domain for biochemical measurement processing

Analog multiplexing in time domain for biochemical measureme...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： A. Patel T. Terry H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory (MSDL) Electrical and Systems Engineering Department Oakland University Rochester MI USA

Digital Multiplexers and Analog multiplexers, through the use of filters and their applications implemented in frequency domain, which requires extensive hardware and is costly have seen substantial amount of research compared to an analog multiplexer in time domain. This Paper Presents design, Simulation, Implementation and Evaluation of a four-to-one analog multiplexer. The analog multiplexer is implemented with the help of four buffers and four transmission gates using 0.35 /spl mu/m CMOS Technology with optimum linear ranges that covers 60% of total input supply voltage. The analog multiplexer is developed for a biochemical preprocessing unit to multiplex time-varying analog input signals coming from real-time sensor arrays and to connect the selected input to one A/D converter for digital implementation of a bio-inspired intelligent signal detection system or to an analog implemented biochemical detection system.

关键词： Time measurement Multiplexing Sensor arrays CMOS technology Intelligent sensors Digital filters Frequency domain analysis Hardware Voltage Data preprocessing

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A formal mapping of static information models into dynamic models for process planning and control purposes

A formal mapping of static information models into dynamic m...

引用

International Workshop on Discrete Event systems, WODES

作者： P. Falkman J. Nielsen B. Lennartson Control and Automation Laboratory Department of Signals and Systems Chalmers University of Technology Gothenburg Sweden Computer Systems for Design and Manufacturing Department of Production Engineering Kungliga Tekniska Högskolan Stockholm Sweden

A formal mapping between static information models and dynamic models is presented. The static information models are given according to an international standard for product, process and resource information exchange. The dynamic models are described as discrete event systems. The product, process and resource information is automatically converted into product routes and used for simulation, controller synthesis and verification. The focus in this paper is on resource booking problems. A high level language, which combines Petri nets and process algebra, is presented and used for specification of desired routes. A main implication of this methodology is to enable the reuse of process information when creating dynamic models for process control. This method also enables simulation and verification to be conducted early in the development.

关键词： Process planning Process control Automatic control Manufacturing systems Petri nets Algebra Signal mapping Manufacturing automation Computer aided manufacturing Manufacturing processes

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A wavelet-based measurement of signal fractal dimensions

A wavelet-based measurement of signal fractal dimensions

引用

Canadian Conference on electrical and Computer engineering (CCECE)

作者： A.Z.R. Langi H.B. Nugraha Laboratory for Signals and Systems Department of Electrical Engineering and IC Design Laboratory IURC Microelectronics DSP Research and Technology Group Bandung Institute of Technology Bandung Jawa Barat Indonesia

This paper describes a study of measuring signal fractal dimensions (especially in a form of Lipschitz exponents /spl gamma/) using wavelets. The procedure is as follows. Given a one-dimensional signal f(t) and its corresponding wavelet transform (at a scale a and a position b) as W/sub f/(a, b), we find wavelet maxima lines l(a, b) and their corresponding wavelet maxima |W/sub f/(a, b)|. Suppose the signal f(t) has a Lipschitz exponent /spl gamma/ at t=b/sub 0/, and there is a maxima line l(a,b) reaching b/sub 0/ as a/spl rarr/0. The corresponding wavelet maxima in the line satisfy an inequality |W/sub f/(a, b)|/spl les/Ca/sup /spl gamma/+0.5/ for some constant C and a/spl rarr/0. A log-log plot on the inequality estimates the Lipschitz exponent /spl gamma/. We have performed an experiment of the procedure for f(t)=1-|0.5-t|/sup /spl gamma//, where the Lipschitz component /spl gamma/ varies from 0.1 to 0.9 at a 0.1 interval. The procedure provides relatively good estimates for 0.5/spl les//spl gamma//spl les/0.9, with relative errors less them 10%.

关键词： Fractals Wavelet transforms Signal processing Laboratories Signal processing algorithms Digital signal processing Microwave integrated circuits Signal design Microelectronics Electric variables measurement

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