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IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： M. Al-Nsour H.S. Abdel-Aty-Zohdy Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

High performance NMOS analog circuits which perform voltage addition, average weighing, and signal scaling are presented. Utilization of these circuits in artificial neural network applications is briefly discussed. The circuits are characterized by a simple structure which offers compactness, low voltage supply, and wide input range. In addition, inputs and outputs are voltages which eliminate the need for current voltage conversion. Hence, reduced power consumption and higher performance is achieved. A two-input analog adder has been accomplished through MOSIS 2.0 /spl mu/m n-well CMOS technology at Orbit Semiconductors, and occupies an area of 135/spl times/145 /spl mu/m/sup 2/. Inputs are within /spl plusmn/3 V for 3.3 V supply. Power consumption is less than 0.5 mW and THD is less than -36 dB. Measurements and performance evaluation are presented.

关键词： Analog computers Computer networks Neural networks Artificial neural networks Energy consumption CMOS technology MOS devices Analog circuits Low voltage Adders

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Parallel implementation of a multialphabet arithmetic coding algorithm

Parallel implementation of a multialphabet arithmetic coding...

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IEE Colloquium on Data Compression: Methods and Implementations (Ref. No. 1999/150)

作者： S. Mahapatra J.L. Nunez C. Foregrino-Thribe S. Jones Loughborough University Electronic Systems Design Laboratory Department of Electronic and Electrical Engineering Loughborough University Loughborough Leicestershire UK

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ANN digitally programmable analog synapse

ANN digitally programmable analog synapse

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： M. Al-Nsour H. Abdel-Aty-Zhody Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA Oakland University Rochester MI US

An Artificial Neural Network (ANN) synapse with local digital weight storage capability is presented. It utilizes a novel, compact, voltage mode multiplying digital-to-analog converter to perform multiplication between an analog input and a digital weight. A 6-bit signed weight synapse chip has been implemented in VLSI through MOSIS 1.2 micrometer n-well CMOS technology. It occupies a total area of 1.35 mm/sup 2/. With +3 Volts supply, the circuit accepts analog inputs within /spl plusmn/1 V. Output is also within /spl plusmn/1 V. Maximum power consumption is 20 mW and total error is less than 3%. Circuit analysis and performance evaluation is presented.

关键词： Voltage Circuits Artificial neural networks Digital-analog conversion CMOS technology Energy consumption Silicon Capacitance Microelectronics Laboratories

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Implementation of programmable digital sigmoid function circuit for neuro-computing

Implementation of programmable digital sigmoid function circ...

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1998 Midwest Symposium on Circuits and systems, MWSCAS 1998

作者： Al-Nsour, Mahmoud Abdel-Aty-zohdy, Hoda S. Department of Electrical and Systems Engineering Microelectronics Systems Design Laboratory Oakland University RochesterMI48309-4401 United States

ISBN: (纸本)0818689145

A programmable digital sigmoid function generator circuit has been designed and implemented. The circuit is based on second order approximation of the nonlinear sigmoid function and utilizing its characteristics. It offers an easy way of changing the steepness of the function in the transition state. In addition, the squaring function operation was implemented using combinational logic. This offers a compact realization of the system as a parallel bit architecture. The maximum output error is.047 and the average error is within 0.01. Simulations show that the circuit operates satisfactorily up to 50 MHz. The digital VLSI circuit has been fabricated using MOSIS/AMI N-well 1.2 μm CMOS double metal process. It occupies an area of 900×450 μm2. © 1999 IEEE.

关键词： Timing circuits

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Verification system interface for VLSI combinational circuits

Verification system interface for VLSI combinational circuit...

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1998 Midwest Symposium on Circuits and systems, MWSCAS 1998

作者： El-Licy, Fatma A. Abdel-Aty-zohdy, Hoda S. Department of Electrical and Systems Engineering Microelectronics System Design Laboratory Oakland University RochesterMI48309-4401 United States

ISBN: (纸本)0818689145

A proof of correctness of a given VLSIC system design is established by proving the consistency and implication of the implemented design with respect to the specified design. The set of conditions that establish such consistency is termed verification conditions (VCs). This paper presents an automatic interface system for the verification of VLSI combinational circuits in which VCs are synthesized from circuit definition. This interface will allow a top down specification of the design (written in a given HDL language) to be parsed into binary tree structure representation. Also, a logical construct is built up from the physical layout specifications of the implemented design (extracted as SPICE file). The top down parse tree along with bottom up logic constructs form the basic building block structure of the front end of the interface system. VCs are then synthesized from the outcomes of the front end through a preprocessor. The back end of the interface system constitutes the preprocessor and a set of designators and modules for manipulating mathematical and logical operations. It provides an environment in which a theorem prover can be used to create a formal proof schema for the VCs which satisfy partial correctness of the circuit under consideration. © 1999 IEEE.

关键词： Specifications

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Timing driven multi-FPGA board partitioning

Timing driven multi-FPGA board partitioning

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International Conference on VLSI design

作者： R. Burra D. Bhatia Design Automation Laboratory Department of Electrical and Computer Engineering and Computer Science University of Cincinnati Cincinnati OH USA

System level design is increasingly turning towards FPGAs to take advantage of their low cost and fast prototyping. In this paper we present a timing driven partitioning approach for an architecturally constrained multi-FPGA system. The partitioning approach uses path-based clustering based on the work by Dennis et al. (1995) and retiming. The board-level architecture is based on the PCB model consisting of four Xilinx 4013 FPGAs. The proposed algorithm has been tested on large scale real designs.

关键词： Timing Field programmable gate arrays System-level design Turning Costs Prototypes Clustering algorithms Partitioning algorithms Testing Large-scale systems

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Wavelet-multifractal processing of signals

Wavelet-multifractal processing of signals

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IEEE Asia-Pacific Conference on Circuits and systems

作者： K. Soemintapura A.Z.R. Langi Laboratory for Signals and Systems Department of Electrical Engineering Institute of Technology Bandung Laboratory of Microelectronics Design IURC Microelectronics Institute of Technology Bandung Bandung West Java Indonesia

This research develops a new approach in processing multimedia signals (i.e., speech, audio, and images) using wavelets and multifractals. Processing multimedia signals is critical in many modern telecommunication and information systems. Nonstationary behaviours have been the most important characteristics of multimedia signals because they carry signal information. Unfortunately nonstationary parts are difficult to process effectively using traditional tools such as Fourier transforms. In contrast, wavelets and multifractality not only reveal that nonstationary parts are sufficient to represent natural images, but also can be used to reconstruct such signals. The general objectives of this research are to develop the wavelet and multifractal concepts into a new signal-processing framework, to obtain more effective and efficient signal representation. If the objectives can be achieved, the results of the proposed research can be a breakthrough in nonstationary signal processing, as fundamental as the well known Fourier approach in stationary signal processing.

关键词： Signal processing Feature extraction Fractals Signal analysis Laboratories Microelectronics Signal synthesis Character recognition Data mining Signal design

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Performance of a dynamic TDMA system for mobile wireless access

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International Journal of Wireless Information Networks 1998年第4期5卷 321-340页

作者： Drakopoulos, Elias Gerakoulis, Diakoumis Lucent Technologies Naperville IL 60566 United States AT and T Laboratories Shannon Laboratory Florham Park NJ 07932 United States Aristotle University of Thessaloniki Greece Northwestern University United States AT and T Bell Laboratories United States Information Technology Center Comp. Sci. and Appl. Math Department Illinois Institute of Technology United States Entpr. Arch. Plan. and Design Center Netwk. Plan. Ctr. of Bell Lab. Lucent Technologies United States New York Institute of Technology United States Polytechnic Institute of New York United States City University of New York United States Electrical Engineering Department Pratt Institute Brooklyn NY United States Ctr. of Excellence in Info. Systems Tennessee State University United States Network Wireless Systems United States

A dynamic TDMA system can utilize voice activity and allow the integration of voice and data traffic. This can be achieved by allocating frequency channels and time slots on demand. In this approach, upon the arrival of a talkspurt or a data packet, the base station is requested to assign a time slot for each transmission. Message requests and assignments of mobile users are carried over a Control channel, while the voice and traffic are transmitted over a Traffic channel. Time slot assignments are made from a 'pool' of Traffic channels. A number of slots in the pool will be shared by voice and data, with voice having priority over data, and the remaining will be used by data only. Voice slots are reserved for the duration of the talkspurt whereas data packets are assigned on a per-slot basis. Data packets can be buffered whereas voice traffic can only tolerate limited delay beyond which talkspurts will be clipped off. The Control channel uplink access is based on Slotted Aloha so that mobile users have autonomous access to base stations. This paper presents the performance of the dynamic TDMA system outlined here. The analysis aims at assessing the capacity gained by using voice activity and voice/data integration, in terms of the impairments introduced to voice quality (e.g., speech clipping and/or delay) and the delays to data packets. The analysis has been based on a discrete time Markov model operating on a frame-by-frame basis that provides the joint distribution of the number of active voice and data users in the system. The analysis also evaluates the delays of message requests via the uplink control channel. In evaluating the clipping probability, we combine the impact of both the access delays at the control channel as well as the unavailability of time slots in the pool. Performance results indicate that the capacity gain may exceed 80% and the speech clipping can be kept below 1%. Also, data packets may be transmitted with limited delays even when all ca

关键词： Time division multiple access

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Classification and compression of ICEGS using Gaussian mixture models

Classification and compression of ICEGS using Gaussian mixtu...

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IEEE Workshop on Neural Networks for Signal Processing

作者： R. Coggins M. Jabri Systems Engineering and Design Automation Laboratory Department of Electrical Engineering University of Sydney Australia

Implantable cardioverter defibrillators (ICD) administer high voltage shock therapies to terminate dangerous cardiac arrhythmias. Improving the functionality of these devices to include online diagnosis based on intracardiac electrogram (ICEG) morphology and to log dangerous signals is important for their more widespread use. It is essential that the ICD implement a signal compression scheme due to the limited memory in the device. We have fitted Gaussian mixture models to the ICEG signals in order to investigate to what extent, nonlinear data models are advantageous in this application compared to the traditional linear approaches used in the field and to explore the common features between classification and compression. Results of fitting the mixture models show that typically a single Gaussian per class for classifiers and single Gaussian prediction models for data compression are adequate data representations provided the data is preprocessed to remove non-stationary behaviour.

关键词： Heart Data compression Morphology Rhythm design engineering systems engineering and theory design automation Laboratories Cardiology Voltage

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Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement 7th

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7th International Workshop on Field Programmable Logic and Applications, FPL 1997

作者： Emmert, John M. Bhatia, Dinesh Design Automation Laboratory Department of Electrical and Computer Engineering and Computer Science University of Cincinnati P.O. Box 210030 CincinnatiOH45221-0030 United States

ISBN: (纸本)3540634657

Field-programmable gate arrays have the potential to provide reconfigurability in the presence of faults. In this paper, we have investigated the problem of partially reconfiguring FPGA mapped designs. We present a maximum matching based algorithm to reconfigure the placement on an FPGA with little or no impact on circuit performance. Experimental results indicate the algorithm works well for both fault tolerance and reconfigurable computing applications. We also present the motivation and feasibility of using a similar approach for dynamic circuit reconfigurability. © Springer-Verlag Berlin Heidelberg 1997.

关键词： Field programmable gate arrays (FPGA)

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