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Proceedings of the 8th International Conference on VLSI design

作者： Bhatia, Dinesh Hardambidest, James Design Automation Laboratory Department of Electrical and Computer Engineering University of Cincinnati ML - 0030 CincinnatiOH45221-0030 United States Department of Mathematics and Computer Science Barry University 11300 NE 2nd Avenue Miami ShoresFL33161-6695 United States

In this paper we prove an fl(n1og n) lower bound on the number of edges of an n-permutation gmph G = (V,E). The lower bound is applicable to and characterizes permutations for Field Progmmmable Interconnection Chips and, more importantly, permutation networks in geneml. We also propose a family of permutation networks as a variation of the known Bened network with a wide mnge of diameters, a network property directly related to routing delays. Finally, the relation between the total number of progmmmable switches and the routing delay (mazimum length of routing paths for specific 1/0 permutations) is explored. © 1995 IEEE Computer Society. All rights reserved.

关键词： Integrated circuit interconnects

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Systematic design of novel architectures for implementation of Radon Transform

Systematic design of novel architectures for implementation ...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： D. Soudris T. Chronopoulos N. Koussoulas T. Stouraitis Department of Electrical & Computer Engineering Democritus University of Thrace Xanthi Greece Lab of Automation and Robotics Department of Electrical Engineering University of Patras Achaia Greece VLSI Design Laboratory Department of Electrical Engineering & Computer Technology University of Patras Achaia Greece

A systematic methodology is introduced for designing highly pipelined array architectures for implementation of Discrete Radon Transform and its Inverse, starting from the algorithmic level and ending with the architectural (hardware) level. Due to large amount of data, the original algorithm is partitioned into nested loops that can be easily mapped onto fixed-size hardware. The proposed methodology derives a plethora of alternative architectures, which meet various parameters such as high-throughput rate, maximum hardware utilization, and pipelinability. Moreover, the derived architectures are piecewise regular and consist of linear and/or 2-D systolic arrays.

关键词： Discrete transforms Computer architecture Algorithm design and analysis Partitioning algorithms Hardware Systolic arrays Geophysics computing Concurrent computing Image reconstruction Robotics and automation

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Feature extraction networks for dull tool monitoring

Feature extraction networks for dull tool monitoring

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： L. Owsley L. Atlas G. Bernard Interactive Systems Design Laboratory Department of Electrical Engineering University of Washington Seattle WA USA Boeing Commercial Airplane Group Seattle WA USA

Automatic feature extraction is a need in many current applications, including the monitoring of industrial tools. Currently available approaches suffer from a number of shortcomings. The Kohonen (1989) self-organizing neural network (SONN) has the potential to act as a feature extractor, but we find it benefits from several modifications. The purpose of these modifications is to cause feature variations to be aligned with the SONN indices so that the indices themselves can be used as measures of the features. The modified SONN is applied to the dull tool monitoring problem, and it is shown that the new algorithm extracts and characterizes useful features of the data.

关键词： Feature extraction Monitoring Frequency Resonance Data mining Spectrogram Principal component analysis Humans Interactive systems Laboratories

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Synthesized passive feedback control of sensor-rich smart structures-experimental results

Synthesized passive feedback control of sensor-rich smart st...

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IEEE Conference on Control Technology and Applications (CCTA)

作者： P. Akella J.T. Wen Control Laboratory for Mechanical Structures Department of Electrical Computer and Systems EngineeringCenter for Advanced Technology in Automation Robotics & Manufacturing Rensselaer Polytechnic Institute RPI Troy NY USA

Passivity based controllers are used in structural control due to their inherent robustness properties. These controllers require sensor/actuator collocation. In this paper, we consider the design of a "squaring down" matrix which renders a system passive by using a linear combination of all collocated and non-collocated sensor/actuator pairs. The design uses experimental transfer functions and does not require the knowledge of the system model. The problem of finding the squaring down matrix is cast as a solution to a set of linear matrix inequalities (LMIs) subject to some additional performance considerations. The design procedure of the squaring down matrix assumes that velocity information is available from the sensors which is not generally the case. We show that the squaring down matrix can be implemented without the use of such velocity information. We provide experimental results gathered from the single link flexible beam setup in the C/sub La/MS laboratory at RPI to show that implementation of passive loops without velocity measurements provides very good results.

关键词： Feedback control Linear matrix inequalities Intelligent sensors Control system synthesis Robust control Sensor systems Hydraulic actuators Transfer functions Laboratories Economic indicators

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Analog signal-selector circuit for quick gas detection from gas-sensor arrays

Analog signal-selector circuit for quick gas detection from ...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： H.S. Abdel-Aty-Zohdy F.A. El-Licy Dept. of Electr. & Syst. Eng. Oakland Univ. Rochester MI USA Microelectronics System Design Laboratory Department of Electrical and Systems Engineering Oakland University Rochester MI USA

A Sixteen Input Maximum/Minimum Analog signal-selector Circuit (SIMMAC) is designed, simulated, and implemented using 2 /spl mu/m p-well (Orbit) CMOS technology. The circuit is useful in recognition of gas types from measurements of thin-film gas-sensor arrays. The output signal of each thin-film gas detector is typically a function of bias voltages, temperature and pressure, film type, frequency, and gas type. Gas sensor arrays provide profiles of resistivity vs. temperature, for a particular PPM, and/or profiles of resistivity vs. pressure at a particular temperature. Since different chemical gas types have peak resistivity values at a certain temperature and a certain pressure, a selector circuit is needed to identify chemical gas components. The SIMMAC design is based on a multiple-input current comparator median circuit. Simulation results gave an accuracy of better than 94% with analog input signal values from 1.6 to 3.6 V. The SIMMAC is suitable for gas detection from a sensor-array of up to 16-elements with known models and negligible signal distortion. Further, it may be used as a post processor to select the winning synapse in an unsupervised neural network for pattern recognition with distorted and unidentified models of gas mixtures.

关键词： Temperature sensors Conductivity Circuit simulation CMOS technology Thin film circuits Gas detectors Sensor arrays Chemicals Signal design CMOS analog integrated circuits

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PARALLEL AND DISTRIBUTED TLM COMPUTATION WITH SIGNAL-PROCESSING FOR ELECTROMAGNETIC-FIELD MODELING

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INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS 1995年第3-4期8卷 169-185页

作者： SO, PPM ESWARAPPA, C HOEFER, WJR NSERC/MPR Teltech Research Chair in RF Engineering Department of Electrical and Computer Engineering University of Victoria Victoria British Columbia V8W 3P6 Canada Poman So received his B.Sc. degree in computer science and physics from the University of Toronto Toronto Onatario Canada in 1985. He obtained his B.A. Sc. and M.A.Sc. degrees in electrical engineering (summa cum laude) from the University of Ottawa Ottawa Ontario Canada in 1987 and 1989 respectively. Mr So was a research engineer in the University of Ottawa from January 1989 to October 1991 his research interests included CAD techniques of microwave circuits and numerical methods for electromagnetic wave modelling. He specialized in the development of electromagnetic engineering CAD software and successfully implemented a number of electromagnetic wave simulators based on the two-dimensional and three-dimensional transmission-line matrix methods. From August 1990 to February 1991 he accompanied Professor W. J. R. Hoefer to Rome Italy and Sophia Antiopolas France. During that time he implemented a parallel version of the 3D-TLM simulator for the CM-2 Connection Machine using C-Star and X Windows Library. He is a research engineer and a Ph.D. student at the University of Victoria Victoria British Columbia Canada. He ported the 2D- and 3D-TLM simulators to DECmpp 1200 massively parallel computer using MPL C and C++. He also combined OSA90/hope a commercially available microwave CAD program with a 2D-TLM simulation module for geometry optimization using the Datapipe technique of OSA90/hope. Recently he has developed a distributed client-server computing technique for the TLM method this technique could accelerate the TLM simulation by more than an order of magnitude. Channabasappa Eswarappa received the M.Tech. degree in electrical engineering from the Indian Institute of Technology Kanpur India in 1983 and Ph. D. degree from the University of Ottawa Canada in 1990. He worked as an Assistant Executive Engineer and later as

This paper describes the implementation of transmission-line matrix (TLM) method algorithms on a massively parallel computer (DECmpp 12000), the technique of distributed computing in the UNIX environment, and the combination of TLM analysis with Prony's method as well as with autoregressive moving average (ARMA) digital signal processing for electromagnetic field modelling. By combining these advanced computation techniques, typical electromagnetic field modelling of microwave structures by TLM analysis can be accelerated by a few orders of magnitude.

关键词： Mathematical models

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CONCURRENT LARGE-SIGNAL SIMULATION OF AN ACTIVE MICROSTRIP ANTENNA

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INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS 1995年第1期8卷 3-12页

作者： MCDOWALL, DS FUSCO, VF High Frequency Electronics Laboratory. Department of Electrical and Electronic Engineering The Queen's University of Belfast Ashby Building Stranmillis Road Belfast BT9 5AH U.K. D. Stewart McDowall was born in Dublin Republic of Ireland in 1967. He received the M. Eng. degree in Electrical and Electronic Engineering from the Queen's University of Belfast in 1990. In the same year he was presented with a Distinction Award from the Departmnet of Education of Northern Ireland and he is currently pursuing his Ph.D. in the Microwave Research Group at Q.U.B. His principal research area is the electromagnetic field mapping of microwave systems using concurrent programming. He is an Associate Member of the Institute of Electrical Engineers. Vincent F. Fusco was educated at the Queens's University of Belfast where he obtained the degree of Ph.D. in 1982. He has worked as a research engineer on short-range radar and radio telemetry systems. Currently he is a reader in Microwave Communications in the School of Electrical engineering and Computer Science the Queen's University of Belfast. His current research interests include non-linear microwave circuit simulatino and concurrent programming techniques for electromagnetic field problems with particular emphasis on EMC applications. He has published numerous research papers in these areas. He is the author of the bookMicrowave Circuits Analysis and Computer Aided Design Prentice-Hall 1987. Dr Fusco is a Chartered Electrical Engineer and a Member of the Institute of Electrical Engineers.

This paper details the use of a circuit-based EM modelling technique combined with a harmonic balance simulator used to model the radiation from the microstrip bodies comprising an active antenna circuit. The modelling approach adopted for the planar bodies in the circuit will be shown to allow the use of concurrent algorithms in order to reduce overall computational time.

关键词： Microstrip antennas

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Low power intracardiac electrogram classification using analogue VLSI 4

Low power intracardiac electrogram classification using anal...

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4th International Conference on Microelectronics for Neural Networks and Fuzzy systems, ICMNN 1994

作者： Coggins, Richard Jabri, Marwan Flower, Barry Pickard, Stephen Systems Engineering and Design Automation Laboratory Department of Electrical Engineering 503 University of Sydney 2006 Australia

ISBN: (纸本)0818667109

A system has been developed for the classification of intracardiac electrograms (ICEG). The system is comprised of an analogue VLSI neural network, an implantable cardioverter defibrillator (ICD) and a PC based software training environment. Analogue implementation techniques were chosen to meet the strict power and area requirements of implantable systems. The robustness of the neural network architecture reduces the impact of noise, drift and offsets inherent in analogue approaches. The neural network chip is a 10:6:3 multilayer perceptron with on chip digital weight storage, a bucket brigade input to feed the ICEG to the network and has a winner take all circuit at the output. The chip was implemented in 1.2 μm CMOS and consumes less than 200 nW maximum average power in an area of 2.2×2.2 mm2. The network was trained in loop with the ICD in the signal processing path. Results are presented, demonstrating the advantages of combining neural network and and low power analogue circuit techniques by distinguishing certain dangerous arrhythmia, not currently possible in existing ICDs. © 1994 IEEE.

关键词： Low power electronics

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Field Programmable Gate Arrays: A cheaper way of customizing product prototypes

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IEEE Potentials 1994年第1期13卷 16-19页

作者： Bhatia, Dinesh Department of Electrical and Computer Engineering Design Automation Laboratory University of Cincinnati

Advances in VLSI technology have brought very complex digital systems onto a very small area of silicon. However, the design cycle times associated with the conventional VLSI designs have called for a technology that will support very rapid system prototyping. Also, the non-recurring engineering (NRE) costs associated with existing VLSI technologies are very high. An ideal design style should support rapid prototyping at almost no or very nominal NRE costs. FPGA is an attempt in this direction. FPGAs have a potential for matching both speed and density of mask programmed gate arrays (MPGAs). It is expected that more and more digital designs will be built on FPGAs, and FPGA based designs will outnumber the MPGA based designs in the near future. The author begins by discussing the nature of FPGAs and their architecture (with design tools). The author goes on to discuss custom computing. © 1994 IEEE.

关键词： Field programmable gate arrays Prototypes Switches Programmable logic arrays Logic devices Wires Costs Application specific integrated circuits Very large scale integration Integrated circuit interconnections

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ICEG Morphology Classification using an Analogue VLSI Neural Network 7

ICEG Morphology Classification using an Analogue VLSI Neural...

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7th International Conference on Neural Information Processing systems, NIPS 1994

作者： Coggins, Richard Jabri, Marwan Flower, Barry Pickard, Stephen Systems Engineering and Design Automation Laboratory Department of Electrical Engineering J03 University of Sydney 2006 Australia

An analogue VLSI neural network has been designed and tested to perform cardiac morphology classification tasks. Analogue techniques were chosen to meet the strict power and area requirements of an Implantable Cardioverter Defibrillator (ICD) system. The robustness of the neural network architecture reduces the impact of noise, drift and offsets inherent in analogue approaches. The network is a 10:6:3 multi-layer perceptron with on chip digital weight storage, a bucket brigade input to feed the Intracardiac Electrogram (ICEG) to the network and has a winner take all circuit at the output. The network was trained in loop and included a commercial ICD in the signal processing path. The system has successfully distinguished arrhythmia for different patients with better than 90% true positive and true negative detections for dangerous rhythms which cannot be detected by present ICDs. The chip was implemented in 1.2um CMOS and consumes less than 200nW maximum average power in an area of 2.2 × 2.2mm2 © NIPS *** rights reserved.

关键词： Network architecture

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