In spite of the impressive progress in the development of the two main methods for formal verification of reactive systems - Symbolic Model Checking and Deductive Verification, they are still limited in their ability ...
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Bounded Model Checking based on SAT methods has recently been introduced as a complementary technique to BDD-based Symbolic Model Checking. The basic idea is to search for a counter ex- ample in executions whose lengt...
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Generalisations of theory change involving operations on arbitrary sets of wffs instead of on belief sets (i.e., sets closed under a consequence relation), have become known as base change. In one view, a base should ...
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Epistemic entrenchment, as presented by Gardenfors and Makinson (1988) and Gardenfors (1988), is a formalisation of the intuition that, when forced to choose between two beliefs, an agent will give up the less entrenc...
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This report presents preliminary results from our project on creating distributed expertise for teaching computer organization & architecture course(s) in the undergraduate computerscience curriculum. We present ...
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ISBN:
(纸本)9781450373586
This report presents preliminary results from our project on creating distributed expertise for teaching computer organization & architecture course(s) in the undergraduate computerscience curriculum. We present the details of an online survey designed to gather information from faculty on the current state of teaching this course. The survey also tries to identify specific areas of need for creating distributed expertise as reported by various faculty. We also present several resources that have been identified that are available for use by faculty teaching the course(s). This report represents a mid-point of an ongoing two-year study. Following a discussion of the currently identified needs, we discuss ways to address them and conclude the report with a plan of action that will follow in the next phase of the project.
A zap is a two-round, witness-indistinguishable protocol in which the first round, consisting of a message from the verifier to the prover, can be fixed "once-and-for-all" and applied to any instance, and wh...
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A zap is a two-round, witness-indistinguishable protocol in which the first round, consisting of a message from the verifier to the prover, can be fixed "once-and-for-all" and applied to any instance, and where the verifier does not use any private coins. We present a zap for every language in NP, based on the existence of non-interactive zero-knowledge proofs in the shared random string model. The zap is in the standard model, and hence requires no common guaranteed random string. We introduce and construct verifiable pseudo-random bit generators (VPRGs), and give a complete existential characterization of both noninteractive zero-knowledge proofs and zaps in terms of approximate VPRGs. We present several applications for zaps; In the timing model of C. Dwork et al. (1998) and using moderately hard functions, we obtain 3-round concurrent zero knowledge and 2-round concurrent deniable authentication (the latter protocol also operates in the resettable model of R. Canetti et al. (2000)). In the standard model we obtain 2-round oblivious transfer using public keys (3-round otherwise). We note that any zap yields resettable 2-round witness-indistinguishability and obtain a 3-round timing-based resettable zero-knowledge argument system for any language in NP.
Usually, realizing self-timed pipelined data-paths for high performance Digital Signal Processors (DSPs) dynamic CMOS logic is used. In this paper a novel methodology to implement computational elements of self-timed ...
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Usually, realizing self-timed pipelined data-paths for high performance Digital Signal Processors (DSPs) dynamic CMOS logic is used. In this paper a novel methodology to implement computational elements of self-timed data-paths is presented. It is based on the use of both static and dynamic CMOS modules. The former act as overlapped execution circuits and they anticipate their computation with respect to the dynamic blocks. The above method applied to a 32-bit addition stage allows a performance gain to be obtained of up to about 40% and a reduction in power dissipation of about 33%, with a reasonable area overhead compared to conventional design.
Performance analysis is an important step in tuning performance critical applications. It is a cyclic process of measuring and analyzing performance data which is driven by the programmers hypotheses on potential perf...
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Performance analysis is an important step in tuning performance critical applications. It is a cyclic process of measuring and analyzing performance data which is driven by the programmers hypotheses on potential performance problems. Currently this process is controlled manually by the programmer. The implicit knowledge applied in this cyclic process must be formalized in order to be reused in the automation of performance analysis tools. This article describes the performance property specification language ASL developed in the APART Esprit IV working group. ASL allows the specification of performance data via an object model and of performance properties via a specially designed notation. Performance bottlenecks can then be identified based on the specification since bottlenecks are viewed as performance properties with a huge negative impact. We present the ASL language in the context of MPI applications.
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