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Machine Learning for the Analysis of Human Microbiome in Inflammatory Bowel Diseases: Literature Review 11th

Machine Learning for the Analysis of Human Microbiome in...

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10th International Conference on Innovation and New Trends in Information Technology, INTIS 2022 and 11th International Conference on Innovation and New Trends in Information Technology, INTIS 2023

作者： En Najih, Nouhaila Moussa, Pr. Ahmed Systems and Data Engineering Team ENSA University Abdelmalek Essaadi Tangier Morocco

ISBN: (纸本)9783031473654

The pathogenesis of inflammatory bowel disease is related to the imbalance of microbial community composition. A reduction in the diversity of the intestinal microbiota as well as specific taxonomic and functional shifts have been reported in inflammatory bowel diseases and may play a central role in the inflammatory process. The aim was to review recent developments in the structural and functional changes observed in the gastrointestinal microbiome in patients with inflammatory bowel diseases and to survey the use of machine learning to discover the microbiome in inflammatory bowel disease. We start by highlighting the relationship between gut microbiome disorder with inflammatory bowel disease including different studies that confirmed this association, then, we provide an overview of the use of Machine Learning in analyzing the microbiome in inflammatory bowel diseases. © 2024, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Machine learning

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Faster R-CNN assessment for air bubbles detection in the conformal coating application

Faster R-CNN assessment for air bubbles detection in the con...

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2021 International Conference on Microelectronics, ICM 2021

作者： Zouhri, Nizar El Mourabit, Aimad El Abidine, Alaoui Ismaili Zine Ensa. Abdelmalek Essaâdi University System Data Engineering Team Tangier Morocco University Mohammed v Information Communication and Embedded Systems Team Rabat Morocco

ISBN: (纸本)9781665408394

The detection of defects in Printed Circuit Boards (PCB) during the assembly process is an important quality requirement for the electronic *** present paper emphasizes the assessment of computer vision implying Faster-RCNN object detection architecture, with the aim of air bubbles defects detection in PCB following the conformal coating *** image configurations have been used to increase artificially the training model's performance, such as air bubbles size, location (on a flat PCB's surface, between components leads) and illumination, *** reaching this cap, we used a random pattern of choice regarding the images with different configurations to properly evaluate its performance, especially the accuracy, precision and *** results showed that Faster-RCNN delivers the lowest detection performance for the air bubbles located between components leads compared to the ones located on flat PCB *** paper shows the accuracy, precision and sensitivity performance results by applying the Faster-RCNN object detection architecture for air bubbles defect detection in the conformal coating application, with aim of providing reference for future research in the field of air bubbles detection. © 2021 IEEE.

关键词： Object detection

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Faster R-CNN assessment for air bubbles detection in the conformal coating application

Faster R-CNN assessment for air bubbles detection in the con...

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International Conference on Microelectronics, ICM

作者： Nizar Zouhri Aimad El Mourabit Alaoui Ismaili Zine El Abidine System & Data Engineering Team Ensa. Abdelmalek Essaâdi University Tangier Morocco Information Communication and Embedded Systems Team University Mohammed V Rabat Morocco

ISBN: (纸本)9781665408400

The detection of defects in Printed Circuit Boards (PCB) during the assembly process is an important quality requirement for the electronic *** present paper emphasizes the assessment of computer vision implying Faster-RCNN object detection architecture, with the aim of air bubbles defects detection in PCB following the conformal coating *** image configurations have been used to increase artificially the training model’s performance, such as air bubbles size, location (on a flat PCB’s surface, between components leads) and illumination, *** reaching this cap, we used a random pattern of choice regarding the images with different configurations to properly evaluate its performance, especially the accuracy, precision and *** results showed that Faster-RCNN delivers the lowest detection performance for the air bubbles located between components leads compared to the ones located on flat PCB *** paper shows the accuracy, precision and sensitivity performance results by applying the Faster-RCNN object detection architecture for air bubbles defect detection in the conformal coating application, with aim of providing reference for future research in the field of air bubbles detection.

关键词： Training Computer vision Sensitivity Printed circuits Lighting Object detection Computer architecture

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Clock Gating Efficiency and Impact on Power Optimization During Synthesis Flow

Clock Gating Efficiency and Impact on Power Optimization Dur...

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International Conference on Microelectronics, ICM

作者： Yassine Attaoui Mohamed Chentouf Zine El Abidine Alaoui Ismaili Aimad El Mourabit Siemens EDA/CSD Calypto - Synthesis Solutions Rabat Morocco System & Data Engineering Team. ENSA of Tangier Abdelmalek Essaâdi University Morocco Information Communication and Embedded Systems (ICES) Team Mohammed V University Rabat Morocco

ISBN: (纸本)9781665408400

Nowadays, power optimization has become an important factor in VLSI design and various low power optimization techniques are being developed. Clock-Gating is considered one of the widely used techniques in VLSI power optimization. Gating the Clock path results in saving power by reducing wasted capacitances switching due to unnecessary activity in logic module paths, thus resulting in more wasted Switching power. Clock gating is not always beneficial, it presents some pitfalls and fallacies within its implementation in various VLSI designs, as well as it doesn't suit all kinds of VLSI logic circuits. In this paper, we measure the impact of the Clock-Gating technique on power as well as on design's performance. We have performed two separate trials, using 112 industrial designs from different technologies, the former trial enables Clock Gate insertion, and the latter does not insert Clock Gate cells in the design's circuitry. We intend to measure the impact of Clock Gating on power by measuring the Power variation and comparing metrics such Instance number Buffer & Inverter, Combinational blocks as well as QoR metrics such Runtime, wire-length, TNS, and Area. Results of this experiment showed that design circuits having Memories (SRAM, DFF, FIFO…) as dominant RTL modules, have the most impact on power when CG cells are inserted. Vice-versa power is less impacted by CG cells insertion for designs that contain microprocessors and datapath blocks as dominant RTL instances.

关键词： Power measurement Runtime Area measurement Switches Very large scale integration Logic gates Sequential circuits

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A new MBFF merging strategy for post-placement power optimization of IoT devices.

A new MBFF merging strategy for post-placement power optimiz...

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ACS/IEEE International Conference on Computer systems and Applications

Recently power has become the most important factor in VLSI design. As clock network is the largest design element in terms of power consumption in modern low-power Very Large Scale Integration (VLSI) Designs and IoT applications, several studies have been made in order to reduce the power leaks and unnecessary switching of the clock network. The clock gating, as well as the use of Multibit Flip Flops (MBFFs), are some of the widely used low-power *** this paper, we presented a novel approach for power consumption reduction in IoT systems by applying an iterative MBFF insertion. we will make several trials on the use of multi-bit Flip-Flops during each phase of logic Synthesis, Placement, and Optimization. In the first trial, we have measured the impact of MBFF merging on power and circuit performance in several development stages using 2-bits and 4-bits MBFFs. In the second trial, we have combined 2-bits and 4-bits MBFFs and measured the power numbers and circuit’s performance. Finally, we have applied an iterative MBFF merging algorithm and measure the PPA (Power, Performance, and Area) impact versus traditional MBFF *** result of this experiment achieved a better total MBFF merging coverage of 76.6%, a good routability maintenance with less congestion, less wire-length by 3.8% leading to a switching power improvement of around 3.3% with no timing and area degradation.

关键词： Degradation Power measurement Power demand Merging Switches Very large scale integration Timing

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