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Platform-based MPEG-4 SOC design for video communications

Journal of VLSI signal processing Systems for signal, Image, and Video Technology 2006年第1期42卷 7-19页

作者： Chang, Yung-Chi Chao, Wei-Min Hsu, Chih-Wei Chen, Liang-Gee Department of Electrical Engineering Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Department of Electrical Engineering GIEE NTU Taipei Taiwan Electronics Research and Service Organization Industrial Technology Research Institute Hsinchu Taiwan IEEE CAS Technical Committee of VLSI Systems and Applications Technical Committee of Visual Signal Processing and Communications IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems IEEE CAS Technical Committee on Multimedia Systems and Applications Phi Tan Phi

An MPEG-4 video coding SOC design is presented in this paper. We adopt platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search and spiral full search is implemented for compromise between compression performance and design cost. The proposed data reuse scheme reduces required memory access bandwidth. For texture coding path, an interleaving DCT/IDCT scheduling with substructure sharing technique is proposed. Several key modules are integrated into an efficient platform in hardware/software co-design fashion. The cost-efficient video encoder SOC consumes 256.8 mW at 40 MHz and achieves real-time encoding of 30 CIF (352×288) frames per second. © Springer Science + Business Media, Inc. 2006.

关键词： Multimedia systems

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designing an embedded video processing camera using a 16-bit microprocessor for a surveillance system

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Journal of VLSI signal processing Systems for signal, Image, and Video Technology 2006年第1期42卷 57-68页

作者： Sato, Koichi Evans, Brian L. Aggarwal, J.K. Department of Electrical and Computer Engineering Computer and Vision Research Center University of Texas at Austin Austin TX 78712 United States Department of Electrical and Computer Engineering Embedded Signal Processing Laboratory University of Texas at Austin Austin TX 78712 United States Department of Electrical and Computer Engineering University of Texas Austin Design and Implementation of Signal Processing Systems Technical Committee IEEE Signal Processing Society IEEE Department of Electrical and Computer Engineering Computer and Vision Research Center IEEE Computer Society

This paper describes the design and implementation of a hybrid intelligent surveillance system that consists of an embedded system and a personal computer (PC)-based system. The embedded system performs some of the image processing tasks and sends the processed data to the PC. The PC tracks persons and recognizes two-person interactions by using a grayscale side view image sequence captured by a stationary camera. Based on our previous research, we explored the optimum division of tasks between the embedded system and the PC, simulated the embedded system using dataflow models in Ptolemy, and prototyped the embedded system in real-time hardware and software using a 16-bit CISC microprocessor. This embedded system processes one 320 × 240 frame in 89 ms, which yields one-third of the rate of 30 Hz video system. In addition, the real-time embedded system prototype uses 5.7 K bytes of program memory, 854 K bytes of internal data memory and 2 M bytes external DRAM. © Springer Science + Business Media, Inc. 2006.

关键词： Microprocessor chips

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A new efficient block-matching algorithm for motion estimation

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Journal of VLSI signal processing Systems for signal, Image, and Video Technology 2006年第1期42卷 21-33页

作者： Mahmoud, Hanan Goel, Sumeer Shaaban, Mohsen Bayoumi, Magdy Faculty of Engineering University of Alexandria University Buildings 9 Albert Street Semouha Alexandria 21321 Egypt Center for Advanced Computer Studies University of Louisiana at Lafayette 110 Rex Street Lafayette LA 70504 Faculty of Engineering University of Alexandria Computer Science Department Department of Computer Engineering Department of Computer Science Center for Advanced Computer Studies University of Louisiana Lafayette Technical Committee on Circuits and Systems for Communication Technical Committee on Signal Processing Design and Implementation Neural Network and the Multimedia Technology Technical Committees University of Louisiana Lafayette

This paper presents a new full-search block-matching algorithm: Multi-stage Interval-based Motion Estimation algorithm (MIME). The proposed algorithm is a block based motion estimation algorithm that utilizes successive elimination technique. We define two approximate functions, as the upper and lower boundaries of the interval that includes the Conventional distortion metric SAD. Each stage in the proposed algorithm;except for the last stage;incorporates low resolution pixels for the boundary functions calculations. The final stage is a full resolution block matching stage. MIME has a high probability of finding the optimal motion vector at any stage of the algorithm. The proposed algorithm reduces the computational complexity by successively eliminating non-candidate blocks from the search window at each stage. This computational reduction leads to enhanced performance in terms of low power consumption and fast motion vector estimation. A low power VLSI implementation of the algorithm is also presented in this paper. Simulation results on benchmark video sequences shows that MIME algorithm eliminates almost 88% of the candidate blocks after only two interval based stages. © Springer Science + Business Media, Inc. 2006.

关键词： Motion estimation

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Special Section on Papers Selected from the 20th Symposium on signal processing - Foreword

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2006年第8期E89A卷 2099-2099页

作者： Kuroda, Ichiro Corporate Business Planning Division NEC Electronics Corporation Japan DIPS (Design and Implemantation of Signal Processing) Technical Committee IEEE Signal Processing Soceity Technical Group on Signal Processing of IEICE IEEE IPSJ Japan

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Considering the alternatives in low-power design

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IEEE Circuits and Devices Magazine 2001年第4期17卷 23-29页

作者： Stouraitis, T. Paliouras, V. Department of Electrical and Computer Engineering University of Patras Greece IEEE Circuits and Systems Society Technical Committee on VLSI Systems and Applications Digital Signal Processing and the Multimedia Systems Committees United States VLSI Design Laboratory ECE Dept. University of Patras Greece Computer Engineering and Informatics Department University of Patras Greece ACM SIAM Technical Chamber of Greece Greece

Recent advances in computer arithmetic offer interesting alternative solutions for low-power design. Depending on an assortment of factors that need to be considered, it is worth evaluating the logarithmic number system (LNS) or the residue number system (RNS) for hardware implementations of computationally intensive tasks. As such, the choice of arithmetic can lead to substantial power savings.

关键词： Integrated circuit layout

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Multidimensional DSP core synthesis for FPGA

Multidimensional DSP core synthesis for FPGA

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作者： McAllister, J. Woods, R. Walke, R. Reilly, D. Queen's University Belfast Queen's Road Queen's Island Belfast BT3 9DT United Kingdom Xilinx Development Corporation 52 Mortonhall Gate Edinburgh EH16 6TJ United Kingdom Queen's University of Belfast United Kingdom IEEE Signal Processing Society Technical Committee for the Design and Implementation of Signal Processing Systems IEE Professional Network on Microelectronics and Embedded Systems

Current rapid synthesis approaches for reusable dedicated hardware components (cores) for digital signal processing systems are ineffective since they fail to capture and exploit the manner in which the resulting components are used as part of a heterogeneous system. This leads to counter-productive core redesign for each use of the core. This paper presents a solution to this issue which combines a novel but intuitive system modeling technique and associated core generation and integration methodology which generates reuable core architectures which may be optimised via algorithm level transformations. For an example design problem, these provide an effective rapid core synthesis and implementation exploration flow which allows a factor 3.9 throughput increase with no extra hardware expense. © 2006 Springer Science + Business Media, LLC.

关键词： Field programmable gate arrays

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AN ARCHITECTURE design APPROACH FOR LARGE SATELLITE NETWORKS

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INTERNATIONAL JOURNAL OF SATELLITE COMMUNICATIONS 1994年第3期12卷 197-210页

作者： COTNER, C INUKAI, T COMSAT World Systems 6560 Rock Spring Drive Bethesda MD 20817 USA. Director Customer Technical Support for COMSAT World Systems. He directs support to U.S. users of the INTELSAT satellite network particularly in the areas of certifying that performance of earth-stations is in accordance with system requirements and in supporting the unique needs of television customers. Mr. Cotner's primary technical interests are earth-station design transmission analysis and high power amplifiers. Mr. Cotner has been with COMSAT for over 25 years. Most recently he served as Director of Technical Liaison and Analysis responsible for much of COMSAT World Systems research and development programme for high-level technical interaction with customers such as AT&T and MCI and for initiatives to improve the quality of international satellite transmission. He has also held technical management positions in COMSAT Laboratories COMSAT General where he was a Division Director Earth Segment Engineering and COMSAT World Systems where he represented the U.S. Signatory on the INTELSAT Board of Governors Technical Advisory Committee for five years. Mr. Cotner is a colonel (retired) in the Signal Corps U.S. Army Reserve where he was assigned to several mobilization positions related to satellite communications including a tour of duty on the Joint Staff. Awarded the degree of B.S.E. (cum-laude) in Electrical Engineering by Princeton University. Mr. Cotner also holds an M.S.E. from Cornell University and is a Commandants List graduate of the U.S. Army Command and General Staff College. He and his wife Sharon live in Silver Spring Maryland. COMSAT Laboratories 22300 COMSAT Drive Clarksburg MD 20871 USA. Received the BS and MS degrees in Communications Engineering from the Tokyo Electrical Engineering College Tokyo Japan and the Ph.D. degree in Electrical Engineering from the City University of New York New York. Dr. Inukai is a Principal Scientist in the Network Technology Division of COMSAT Laboratories. He directs res

designing a world-wide satellite network that consists of hundreds of user sites and thousands of circuit connections is a complex problem, which involves selecting a set of candidate satellites and satellite beams/frequency bands from among numerous existing and planned satellites, evaluation of circuit connectivity, earth-station compatibility and sizing, and estimating transponder loading. The design process may also require assessment of the impact of a different set of satellites and modified user traffic requirements on the space segment, the earth-station types and quantity, and the total system cost. Although a conventional design approach based on link-by-link and site-by-site analysis provides accurate results, it is time-consuming and impractical for developing high-level network architectures in a time-constrained environment. A design technique is proposed which employs a set of rules for satellite network design, in combination with extensive databases of satellite parameters, earth-station parameters and user traffic requirements, to synthesize a network architecture. The technique is particularly useful for performing high-level trade-offs among alternative architectures in terms of space segment requirements, the number and type of earth-stations and overall system cost. Once the desired architecture has been selected, a detailed design may be developed using conventional methods.

关键词： SATELLITE NETWORK design RULE-BASED design FIXED SATELLITE SERVICES FDMA INTELSAT BANDWIDTH REQUIREMENTS TRANSPONDER CAPACITY

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Self-Awareness for Autonomous Systems

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PROCEEDINGS OF THE IEEE 2020年第7期108卷 971-975页

作者： Dutt, Nikil Regazzoni, Carlo S. Rinner, Bernhard Yao, Xin Nikil Dutt (Fellow IEEE) received the Ph.D. degree from the University of Illinois at Urbana–Champaign Champaign IL USA in 1989.""He is currently a Distinguished Professor of computer science (CS) cognitive sciences and electrical engineering and computer sciences (EECS) with the University of California at Irvine Irvine CA USA. He is a coauthor of seven books. His research interests include embedded systems electronic design automation (EDA) computer architecture distributed systems healthcare Internet of Things (IoT) and brain-inspired architectures and computing.""Dr. Dutt is a Fellow of ACM. He was a recipient of the IFIP Silver Core Award. He has received numerous best paper awards. He serves as the Steering Committee Chair of the IEEE/ACM Embedded Systems Week (ESWEEK). He is also on the steering organizing and program committees of several premier EDA and embedded system design conferences and workshops. He has served on the Editorial Boards for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems and the ACM Transactions on Embedded Computing Systems and also previously served as the Editor-in-Chief (EiC) for the ACM Transactions on Design Automation of Electronic Systems. He served on the Advisory Boards of the IEEE Embedded Systems Letters the ACM Special Interest Group on Embedded Systems the ACM Special Interest Group on Design Automationt and the ACM Transactions on Embedded Computing Systems. Carlo S. Regazzoni (Senior Member IEEE) received the M.S. and Ph.D. degrees in electronic and telecommunications engineering from the University of Genoa Genoa Italy in 1987 and 1992 respectively.""He is currently a Full Professor of cognitive telecommunications systems with the Department of Electrical Electronics and Telecommunication Engineering and Naval Architecture (DITEN) University of Genoa and a Co-Ordinator of the Joint Doctorate on Interactive and Cognitive Environments (JDICE) international Ph.D. course started initially as EU Erasmus Mundus Project and

Autonomous systems are able to make decisions and potentially take actions without direct human intervention, which requires some knowledge about the system and its environment as well as goal-oriented reasoning. In computer systems, one can derive such behavior from the concept of a rational agent with autonomy (“control over its own actions”), reactivity (“react to events from the environment”), proactivity (“act on its own initiative”), and sociality (“interact with other agents”) as fundamental properties \n[1]\n. Autonomous systems will undoubtedly pervade into our everyday lives, and we will find them in a variety of domains and applications including robotics, transportation, health care, communications, and entertainment to name a few. \nThe articles in this month’s special issue cover concepts and fundamentals, architectures and techniques, and applications and case studies in the exciting area of self-awareness in autonomous systems.

关键词： Special issues and sections Autonomous systems Self-aware Robot sensing systems Computational modeling

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ISDN LOOP EXTENSION USING A MID-SPAN AMPLIFIER

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INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS 1995年第3期8卷 219-224页

作者： ERKER, GJ DODDS, DE KRZYMIEN, WA David E. Dodds was born in Saskatoon Canada in 1945. He received the B. Eng. and MSc. degrees from the University of Saskatchewan in 1966 and 1968 respectively. He worked with Bell Northern Research (Ottawa) on PBX design in 1969 1972 and 1978. Since 1969 he has been with the University of Saskatchewan where he is currently Professor of Electrical Engineering. He teaches courses in electronics and communications and also presents short courses on the fundamentals of telephony. Current research interests are in data transmission signal processing architecture and frame synchronization for PCM and spread spectrum systems. He has been granted five patents relating to commercial products in delta-modulation telephone line interfacing and computer data transmission. In 1986 he was on sabbatical leave at BNR Inc. and worked with an ANSI committee on the standardization of FDDI-II a combined voice and data system. Mr. Dodds is a Registered Consulting Engineer in Saskatchewan. Witold A. Krzyden received his MSc. (Eng.) and Ph.D. degrees (both in Electrical Engineering) in 1970 and 1978 respectively from the Poznan Technical University in Poznan Poland. He was awarded the Minister's of Science and Technology Prize of Excellence for his Ph.D. thesis. From 1970 to 1978 he was a Research Engineer and Teaching Assistant and then from 1978 to 1980 an Assistant Professor of Electrical Engineering at the Poznan Technical University. In 1980 he won a Dutch Government Research Fellowship at the Twente University of Technology in Enschede the Netherlands for the year of 1980/1981. In the following year of 1981/82 he was a Research Assistant Professor there. From 1982 to 1986 he was an Assistant Professor of Electrical Engineering at Lakehead University in Thunder Bay Ontario Canada. In 1986 he joined the Univeristy of Alberta and Alberta Telecommunications Research Centre (now Telecommunications Research Laboratories or TRLabs) as an Associate Professor of Electrical Engineering. Currently he is a Professor of E

The 5.5 km range of the basic rate ISDN loop has been extended by using a negative impedance amplifier and by using a 2 wire/4 wire (2w/4w) amplifier. The negative impedance amplifier extends the range of the loop by 1.0 km, whereas the 2w/4w amplifier extends the range by 1.5 km at the expense of increased complexity. As part of the amplifer design, a resistor/capacitor network has been developed which closely matches the characteristic impedance of telephone cable. Error rate tests have been conducted using various lengths of cable and an operating ISDN line.

关键词： ISDN PHYSICAL LAYER BASIC RATE LOOP RANGE EXTENSION

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ASYNCHRONOUS TRANSFER MODE (ATM) OPERATION VIA SATELLITE - ISSUES, CHALLENGES AND RESOLUTIONS

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INTERNATIONAL JOURNAL OF SATELLITE COMMUNICATIONS 1994年第3期12卷 211-222页

作者： CHITRE, DM GOKHALE, DS HENDERSON, T LUNSFORD, JL MATHEWS, N COMSAT Laboratories 22300 Comsat Drive Clarksburg MD 20871 USA. Received his B.Sc. from the University of Bombay India an M.A. in mathematics from the University of Cambridge U.K. and a Ph.D. in physics from the University of Maryland. He is currently an Associate Executive Director of the Network Technology Division at COMSAT Laboratories. He has been involved in research and development activities in ISDN VSAT networks data communications and network systems and architectures. Prior to his current positions Dr. Chitre was a Principal Scientist in the Network Technology Division at COMSAT Laboratories. Dr. Chitre joined COMSAT Laboratories in 1980. He has made major contributions to the analysis and architecture of data communication ISDN and BISDN via satellite. Dr. Chitre directs and participates in the international and national standards activities in ISDN BISDN and data communication as they apply to satellite communication. He was Chairman of the Working Group on Protocols and Network Timing Function of the CCIR/CCITT Joint Ad Hoc Group on ISDN-Satellite Matters during 1990–1992. Currently he is the Chairman of the Working Group on New Technologies in the ITU Intersector Coordinating Group (ICG) on Satellite Matters. Dr. Chitre was a programme manager during 1990 and 1991 on a contract from INTELSAT on systems studies on satellite communications systems architectures for ISDN and broadband ISDN systems. Currently he is the technical manager of the DoD Contract on ATM via satellite demonstration and the programme manager for the INTELSAT contract on analysis and top-level specification of INTELSAT ISDN subnetworks and SDH compatible transport network. Department manager for ISDN/Data Communications in the Network Technology Division of COMSAT Laboratories. His responsibilities include managing the implementation of next generation telecommunication systems for fixed and mobile satellite systems. Current projects include the development of a high data rate gateway switch that provides for the

Key issues regarding the operation of the broadband integrated services digital network (BISDN) via satellite are presented herein. The specific issues, challenges, and their resolutions are detailed. In particular, the impact of error characteristics and propagation delay on the operation of BISDN via satellite is discussed. Solutions are presented for removing adverse effects and providing high-quality service to users of BISDN via satellite.

关键词： ATM BISDN

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