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Proceedings of the 33rd Australian Conference on Human-computer Interaction

作者： Phillip Gough A. Baki Kocaballi Khushnood Z. Naqshbandi Karen Cochrane Kristina Mah Ajit G. Pillai Yeliz Yorulmaz Ainnoun Kornita Deny Naseem Ahmadpour Affective Interactions Lab School of Architecture Design and Planning The University of Sydney Australia School of Computer Science University of Technology Sydney Australia School of IT Carleton University Canada Affective Interactions Lab The university of Sydney Australia Independent Artist Australia School of Computer Science University of Technology Sydney Australia Affective Interactions lab School of Architecture Design and Planning The University of Sydney Australia

ISBN: (纸本)9781450395984

technology probes are low-fidelity devices that can be used to understand research participant’s lived experiences, but they are not usually subject to iterative design. There are opportunities in human-computer interaction to develop technology probes through co-design, by including diverse perspectives during probe development. To explore this opportunity, five design researchers with different disciplinary and cultural backgrounds engaged with a technology probe to support daily reflections, discussed new directions in a co-design workshop and developed narratives to negotiate possibilities of the probe. This paper presents observations described by each of the researchers using the probe, and insights from the process we followed. We discuss how the the designers’ postitionalities are reflected in the processes, and how they brought value by shaping narratives of the different roles a technology probe might take. We also discuss how we may use co-design of technology probes as a generative method, highlight the importance of open-endedness in the process, and reflect on lessons learned.

关键词： reflection technology probes positionality co-design

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Towards AER VITE: building spike gate signal

Towards AER VITE: building spike gate signal

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IEEE International Conference on Electronics, Circuits and Systems

作者： Fernando Perez-Pena Arturo Morgado-Estevez Carlos Rioja-Del-Rio Alejandro Linares-Barranco Angel Jimenez-Fernandez Juan Lopez-Coronado Jose Luis Munoz-Lozano Applied Robotics Lab High School of Engineering University of Cadiz Department of Computer Architecture and Technology ETSI Computer Science University of Seville Automatic and System Engineering Department University Polytechnics of Cartagena

ISBN: (纸本)9781467312615

Neuromorphic engineers aim to mimic the precise and efficient mechanisms of the nervous system to process information using spikes from sensors to actuators. There are many available works that sense and process information in a spike-based way. But there are still several gaps in the actuation and motor control field in a spike-based way. Spike-based Proportional-Integrative-Derivative controllers (PID) are present in the literature. On the other hand, neuro-inspired control models as VITE (Vector Integration To End point) and FLETE (Factorization of muscle Length and muscle Tension) are also present in the literature. This paper presents another step toward the spike implementation of those neuro-inspired models. We present a spike-based ramp multiplier. VITE algorithm generates the way to achieve a final position targeted by a mobile robotic arm. The block presented is used as a gate for the way involved and it also puts the incoming movement on speed with a variable slope profile. Only spikes for information representation were used and the process is in real time. The software simulation based on Simulink and Xilinx System Generator shows the accurate adjust to the traditional processing for short time periods and the hardware tests confirm and extend the previous simulated results for any time. We have implemented the spikes generator, the ramp multiplier and the low pass filter into the Virtex-5 FPGA and connected this with an USB-AER (Address Event Representation) board to monitor the spikes.

关键词： spike spikes spikes Road gates Hardware Test Information representation Processing information ANION EXCHANGE RESIN Proportional Integral Derivative Control Activation Pelvic Inflammatory Disease RAMP Ramps Multiplying circuits

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Width minimization of two-dimensional CMOS cells using integer programming 96

Width minimization of two-dimensional CMOS cells using integ...

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Proceedings of the 1996 IEEE/ACM international conference on computer-aided design

作者： Avaneendra Gupta John P. Hayes Advanced Computer Architecture Lab. Dept. of Electrical Engr. and Computer Science The University of Michigan Ann Arbor MI and Design Technology Division Intel Corporation 2200 Mission College Blvd. Santa Clara CA Advanced Computer Architecture Lab. Dept. of Electrical Engr. and Computer Science The University of Michigan Ann Arbor MI

ISBN: (纸本)9780818675973

We address the problem of CMOS cell width minimization in the general two-dimensional (2-D) layout style and propose a novel technique based on integer linear programming (ILP) to solve it exactly. We formulate a 0-1 ILP model whose solution minimizes cell width along with the routing complexity across the diffusion rows. We present experimental results that evaluate the performance of two ILP solvers that have very different solution methods, and assess the effect of the number of rows on cell width. Run-times for optimal layouts are in seconds for cells with up to 20 transistors. For larger cells, we propose a practical circuit pre-processing scheme that dramatically reduces the run time with little or no loss in optimality.

关键词： CMOS networks

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Fault Tolerance Research of Visual Convolutional Neural Networks Based on Soft Errors

Fault Tolerance Research of Visual Convolutional Neural Netw...

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IEEE Information technology, Networking, Electronic and Automation Control Conference

作者： Xiaotong Xu Yuzhuo Fu Ting Liu Hongjun You Intelligent Computer Architecture Technology(iCAT) Lab of School of Microelectronics Shanghai JiaoTong University Shanghai China Key Laboratory of Intelligent Computing Technology (SAST) Shanghai Aerospace Electronic Technology Institute Shanghai China

ISBN: (数字)9781728143903

ISBN: (纸本)9781728143910

Injecting faults to the system architecture layer and studying the upper neural network for fault tolerancehe is difficult and time-consuming. This paper proposes an automatic method covering time and space, which can inject faults into the processor on the Simics simulation platform, simulating soft errors, and then collect the time sequence data of the system architecture layer and the observed node data of visual convolutional neural networks program layer. At the same time, combined with the relevant standards, the GAN classifier is used to calibrate the different fault models after converting time sequence data into time sequence images. Finally, the Bayesian network is used to form the path of fault propagation from the architecture layer to the program layer and the result layer. After intensive fault injection into critical registers, the probability of neural network failure caused by soft errors is effectively stimulated.

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High performance sockets and RPC over virtual interface (VI) architecture 3rd

High performance sockets and RPC over virtual interface (VI)...

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3rd International Workshop on Communication, architecture and Applications for Network-based Parallel Computing , CANPC 1999

作者： Shah, Hemal V. Pu, Calton Madukkarumukumana, Rajesh S. M/S CO3-202 Server Architecture Lab Intel Corporation 5200 N.E. Elam Young Pkwy HillsboroOR97124 United States Department of Computer Science and Engineering Oregon Graduate Institute of Science and Technology P.O. Box 91000 PortlandOR97291 United States

ISBN: (纸本)3540659153

Standard user-level networking architecture such as Virtual Interface (VI) architecture enables distributed applications to perform low overhead communication over System Area Networks (SANs). This paper describes how high-level communication paradigms like stream sockets and remote procedure call (RPC) can be efficiently built over user-level networking architectures. To evaluate performance benefits for standard client-server and multi-threaded environments, our focus is on off-the-shelf sockets and RPC interfaces and commercially available VI architecture based SANs. The key design techniques developed in this research include credit-based flow control, decentralized user-level protocol processing, caching of pinned communication buffers, and deferred processing of completed send operations. The one-way bandwidth achieved by stream sockets over VI architecture was 3 to 4 times better than the same achieved by running legacy protocols over the same interconnect. On the same SAN, high-performance stream sockets and RPC over VI architecture achieve significantly better (between 2-3x) latency than conventional stream sockets and RPC over standard network protocols in Windows NTTM 4.0 environment. Furthermore, our high-performance RPC transparently improved the network performance of Distributed Component Object Model (DCOM) by a factor of 2 to 3. © Springer-Verlag Berlin Heidelberg 1999.

关键词： Network architecture

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Testing an evolutionary portfolio algorithm on the CEC2016 real-parameter single objective optimization

Testing an evolutionary portfolio algorithm on the CEC2016 r...

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Congress on Evolutionary Computation

作者： Junyan Yi He Zheng Gang Yang Department of Computer Science and Technology Beijing University of Civil Engineering and Architecture Beijing China Department of Information Renmin University of China Multimedia Computing Lab Beijing China

ISBN: (纸本)9781509006243

In order to take advantages of evolutionary algorithms inspired by different biological evolutions, varieties of approaches have been proposed to combine them together. One of them is the portfolio approach, which keeps choosing a component algorithm from a portfolio of evolutionary algorithms (EAs) to run during the optimizing process. In our approach, each component algorithm has its own population and runs independently without information exchange. At the beginning of each generation, only the component algorithm with the best predicted performance is allowed to run. The proposed portfolio approach is tested on the CEC2016 real-parameter single objective optimization benchmarks. The results show that it is competitive.

关键词： Prediction algorithms Convergence Portfolios Sociology Statistics Iron Optimization

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Dynamic Bayesian brain network partition and connectivity change point detection 5

Dynamic Bayesian brain network partition and connectivity ch...

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5th IEEE International Conference on Computational Advances in Bio and Medical Sciences, ICCABS 2015

作者： Lian, Zhichao Li, Xiang Pan, Yi Guo, Xuan Chen, Le Chen, Guantao Zhihui, Wei Liu, Tianming Zhang, Jing School of Computer Science and Engineering Nanjing University of Science and Technology Nanjing China Department of Mathematics and Statistics Georgia State University AtlantaGA United States Department of Statistics Yale University New HavenCT United States Cortical Architecture Imaging and Discovery Lab Department of Computer Science University of Georgia AthensGA United States Department of Computer Science Georgia State University AtlantaGA United States Department of Biology Georgia State University AtlantaGA United States

ISBN: (纸本)9781467396639

Multiple recent neuroimaging studies revealed that functional interactions within brain regions are locally clustered into small sub-networks where different dynamics of functional interaction occur. However, integration models investigating such functional brain dynamics have been rarely explored. In this paper, a novel Bayesian inference model is developed to partition the brain regions into different sub networks and to simultaneously segment temporal sequence of each sub network into several quasi-stable blocks based on the interaction dynamics among regions. The proposed model has been evaluated and validated by two different simulation models. Also, the model has been applied to a working-memory task-based fMRI dataset and interesting results on both dynamic sub networks and change points were obtained. © 2015 IEEE.

关键词： Dynamics

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Redundant and Loosely Coupled LiDAR-Wi-Fi Integration for Robust Global Localization in Autonomous Mobile Robotics

arXiv

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arXiv 2023年

作者： Stathoulopoulos, Nikolaos Pagliari, Emanuele Davoli, Luca Nikolakopoulos, George The Robotics and AI Group Department of Computer Electrical and Space Engineering Luleå University of Technology Luleå97187 Sweden Lab Department of Engineering and Architecture University of Parma Parma43124 Italy

This paper presents a framework addressing the challenge of global localization in autonomous mobile robotics by integrating LiDAR-based descriptors and Wi-Fi fingerprinting in a pre-mapped environment. This is motivated by the increasing demand for reliable localization in complex scenarios, such as urban areas or underground mines, requiring robust systems able to overcome limitations faced by traditional Global Navigation Satellite System (GNSS)-based localization methods. By leveraging the complementary strengths of LiDAR and Wi-Fi sensors used to generate predictions and evaluate the confidence of each prediction as an indicator of potential degradation, we propose a redundancy-based approach that enhances the system’s overall robustness and accuracy. The proposed framework allows independent operation of the LiDAR and Wi-Fi sensors, ensuring system redundancy. By combining the predictions while considering their confidence levels, we achieve enhanced and consistent performance in localization tasks. Copyright © 2023, The Authors. All rights reserved.

关键词： Forecasting

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yaSpMV: Yet Another SpMV Framework on GPUs

yaSpMV: Yet Another SpMV Framework on GPUs

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作者： Yan, Shengen Li, Chao Zhang, Yunquan Zhou, Huiyang Institute of Software Chinese Academy of Sciences University of Chinese Academy of Sciences Beijing China North Carolina State University RaleighNC United States North Carolina State University RaleighNC United States State Key Lab of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Institute of Software Chinese Academy of Sciences Beijing China

SpMV is a key linear algebra algorithm and has been widely used in many important application domains. As a result, numerous attempts have been made to optimize SpMV on GPUs to leverage their massive computational throughput. Although the previous work has shown impressive progress, load imbalance and high memory bandwidth remain the critical performance bottlenecks for SpMV. In this paper, we present our novel solutions to these problems. First, we devise a new SpMV format, called blocked compressed common coordinate (BCCOO), which uses bit flags to store the row indices in a blocked common coordinate (COO) format so as to alleviate the bandwidth problem. We further improve this format by partitioning the matrix into vertical slices to enhance the cache hit rates when accessing the vector to be multiplied. Second, we revisit the segmented scan approach for SpMV to address the load imbalance problem. We propose a highly efficient matrix-based segmented sum/scan for SpMV and further improve it by eliminating global synchronization. Then, we introduce an auto-tuning framework to choose optimization parameters based on the characteristics of input sparse matrices and target hardware platforms. Our experimental results on GTX680 GPUs and GTX480 GPUs show that our proposed framework achieves significant performance improvement over the vendor tuned CUSPARSE V5.0 (up to 229% and 65% on average on GTX680 GPUs, up to 150% and 42% on average on GTX480 GPUs) and some most recently proposed schemes (e.g., up to 195% and 70% on average over clSpMV on GTX680 GPUs, up to 162% and 40% on average over clSpMV on GTX480 GPUs). © 2014 ACM.

关键词： Graphics processing unit

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Efficient Parallelization of a Protein Sequence Comparison Algorithm on Manycore architecture

Efficient Parallelization of a Protein Sequence Comparison A...

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IEEE International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Xiaochun Ye Van Hoa Nguyen Dominique Lavenier Dongrui Fan Chinese Academy of Sciences Beijing China Key Lab of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China CNRS IRISA/INRIA Rennes France

This paper introduces the Godson-T manycore architecture and demonstrates the efficiency of its synchronization mechanism through a computation intensive bioinformatics application: the comparison of protein banks. The parallel part of the protein sequence comparison algorithm can nearly get a linear speed-up thanks to a fine tuning of the synchronization mechanism provided by the Godson-T chip.

关键词： Protein sequence Bioinformatics computer architecture Genomics Databases Tiles computer displays Scanning probe microscopy Distributed computing Application software

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