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A fast linear-space sequence alignment algorithm with dynamic parallelization framework

A fast linear-space sequence alignment algorithm with dynami...

引用

IEEE 9th International Conference on computer and Information technology, CIT 2009

作者： Xiaochun, Ye Dongrui, Fan Wei, Lin Key Lab of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

Exact pairwise sequence alignment algorithms using dynamic programming require quadratic space and time, and this makes these algorithms impractical for large-scale sequences. In this paper, we propose and evaluate a new Anti-Diagonal based Parallel Linear-Space Algorithm (AD-PLSA). It records similarity matrix scores and start points on special anti-diagonals instead of special rows or columns. This algorithm is able to further reduce the total amount of re-computation. It also produces balanced sub-problems with approximately even size, and this is of great benefit to the parallelization. In addition, we establish a dynamic parallelization framework for the efficient acceleration on a symmetric multiprocessor (SMP) platform. The experimental results present liner speedup for long real DNA sequences. Compared with the typical row-col algorithm, our method is able to save more than 30% of the re-computation, and run twice as fast in the backward phase. © 2009 IEEE.

关键词： DNA sequences

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Sub-sentence division for tree-based machine translation

Sub-sentence division for tree-based machine translation

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Joint Conference of the 47th Annual Meeting of the Association for Computational Linguistics and 4th International Joint Conference on Natural Language Processing of the AFNLP, ACL-IJCNLP 2009

作者： Xiong, Hao Xu, Wenwen Mi, Haitao Liu, Yang Liu, Qun Key Lab. of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences P.O. Box 2704 Beijing 100190 China Key Lab. of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences P.O. Box 2704 Beijing 100190 China

ISBN: (纸本)9781617382581

Tree-based statistical machine translation models have made significant progress in recent years, especially when replacing 1-best trees with packed forests. However, as the parsing accuracy usually goes down dramatically with the increase of sentence length, translating long sentences often takes long time and only produces degenerate translations. We propose a new method named subsentence division that reduces the decoding time and improves the translation quality for tree-based translation. Our approach divides long sentences into several sub-sentences by exploiting tree structures. Large-scale experiments on the NIST 2008 Chinese-to-English test set show that our approach achieves an absolute improvement of 1.1 BLEU points over the baseline system in 50% less time. © 2009 ACL and AFNLP.

关键词： Machine translation

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Accurate, scalable and informative design space exploration for large and sophisticated multi-core oriented architectures

Accurate, scalable and informative design space exploration ...

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International Symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Chang-Burm Cho James Poe Tao Li Jingling Yuan Intelligent Design of Efficient Architecture Lab IDEAL Department of ECE University of Florida Gainesville FL USA Computer Science and Technology School Wuhan University of Technology Wuhan China

ISBN: (纸本)9781424449279

As microprocessors become more complex, early design space exploration plays an essential role in reducing the time to market and post-silicon surprises. The trend toward multi-/many- core processors will result in sophisticated large-scale architecture substrates (e.g. non-uniformly accessed caches interconnected by network-on-chip) that exhibit increasingly complex and heterogeneous behavior. While conventional analytical modeling techniques can be used to efficiently explore the characteristics (e.g. IPC and power) of monolithic architecture design, existing methods lack the ability to accurately and informatively forecast the complex behavior of large and distributed architecture substrates across the design space. This limitation will only be exacerbated with the rapidly increased integration scale (e.g. number of cores per chip). In this paper, we propose novel, multi-scale 2D predictive models which can efficiently reason the characteristics of large and sophisticated multi-core oriented architectures during the design space exploration stage without using detailed cycle-level simulations. Our proposed techniques employ 2D wavelet multiresolution analysis and neural network regression modeling. We extensively evaluate the efficiency of our predictive models in forecasting the complex and heterogeneous characteristics of large and distributed shared cache interconnected by a network on chip in multi-core designs using both multi-programmed and multithreaded workloads. Experimental results show that the models achieve high accuracy while maintaining low complexity and computation overhead. Through case studies, we demonstrate that the proposed techniques can be used to informatively explore and accurately evaluate global, cooperative multi-core resource allocation and thermal-aware designs that cannot be achieved using conventional design exploration methods.

关键词： Space exploration Predictive models Network-on-a-chip Design methodology Microprocessors Time to market Large-scale systems Analytical models Wavelet analysis Multiresolution analysis

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Efficient Parallelization of a Protein Sequence Comparison Algorithm on Manycore architecture

Efficient Parallelization of a Protein Sequence Comparison A...

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IEEE International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Xiaochun Ye Van Hoa Nguyen Dominique Lavenier Dongrui Fan Chinese Academy of Sciences Beijing China Key Lab of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China CNRS IRISA/INRIA Rennes France

This paper introduces the Godson-T manycore architecture and demonstrates the efficiency of its synchronization mechanism through a computation intensive bioinformatics application: the comparison of protein banks. The parallel part of the protein sequence comparison algorithm can nearly get a linear speed-up thanks to a fine tuning of the synchronization mechanism provided by the Godson-T chip.

关键词： Protein sequence Bioinformatics computer architecture Genomics Databases Tiles computer displays Scanning probe microscopy Distributed computing Application software

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A service-oriented priority-based resource scheduling scheme for virtualized utility computing 08

引用

Proceedings of the 15th international conference on High performance computing

作者： Ying Song Yaqiong Li Hui Wang Yufang Zhang Binquan Feng Hongyong Zang Yuzhong Sun Key Lab. of Computer System and Architecture Inst. of Computing Techn. Chinese Academy of Sciences China and National Research Center for Intelligent Computing Systems ICT China and Graduate Univ. of Chinese Academy of Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China and National Research Center for Intelligent Computing Systems ICT China

ISBN: (纸本)9783540898931

In order to provide high resource utilization and QoS assurance inutility computing hosting concurrently various services, this paper proposes aservice computing framework-RAINBOW for VM(Virtual Machine)-basedutility computing. In RAINBOW, we present a priority-based resourcescheduling scheme including resource flowing algorithms (RFaVM) to optimizeresource allocations amongst services. The principle of RFaVM is preferentiallyensuring performance of some critical services by degrading of others to someextent when resource competition arises. Based on our prototype, we evaluateRAINBOW and RFaVM. The experimental results show that RAINBOWwithout RFaVM provides 28%-324% improvements in service performance,and 26% higher the average CPU utilization than traditional service computingframework (TSF) in typical enterprise environment. RAINBOW with RFaVMfurther improves performance by 25%-42% for those critical services whileonly introducing up to 7% performance degradation to others, with 2%-8%more improvements in resource utilization than RAINBOW without RFaVM.

关键词： resource scheduling utility computing virtualization

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McRT-malloc - A scalable transactional memory allocator 06

McRT-malloc - A scalable transactional memory allocator

引用

ISMM 2006 - 2006 International Symposium on Memory Management

作者： Hudson, Richard L. Saha, Bratin Adl-Tabatabai, Ali-Reza Hertzberg, Benjamin C. Programming System Lab Microprocessor Technology Lab Intel Corporation Computer Architecture Lab Stanford University Palo Alto CA

ISBN: (纸本)1595932216

Emerging multi-core processors promise to provide an exponentially increasing number of hardware threads with every generation. Applications will need to be highly concurrent to fully use the power of these processors. To enable maximum concurrency, libraries (such as malloc-free packages) would therefore need to use non-blocking algorithms. But lock-free algorithms are notoriously difficult to reason about and inappropriate for average programmers. Transactional memory promises to significantly ease concurrent programming for the average programmer. This paper describes a highly efficient non-blocking malloc/free algorithm that supports memory allocation and deallocation inside transactional code blocks. Thus this paper describes a memory allocator 1 that is suitable for emerging multicore applications, while supporting modem concurrency constructs. This paper makes several novel contributions. It is the first to integrate a software transactional memory system with a malloc/free based memory allocator. We present the first algorithm which ensures that space allocated in an aborted transaction is properly freed and does not lead to a space blowup. Unlike previous lock-free malloc packages, our algorithm avoids atomic operations on typical code paths, making our algorithm substantially more efficient. Copyright © 2006 ACM.

关键词： Storage allocation (computer)

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McRT-STM: A high performance software transactional memory system for a multi-core runtime

McRT-STM: A high performance software transactional memory s...

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2006 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP'06

作者： Saha, Bratin Adl-Tabatabai, Ali-Reza Hudson, Richard L. Chi, Cao Minh Hertzberg, Benjamin Programming System Lab. Microprocessor Technology Lab. Intel Corporation Computer Architecture Lab. Stanford University Palo Alto CA

ISBN: (纸本)1595931899

Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed this concurrency using locks (mutex based synchronization). Unfortunately, lock based synchronization often leads to deadlocks, makes fine-grained synchronization difficult, hinders composition of atomic primitives, and provides no support for error recovery. Transactions avoid many of these problems, and therefore, promise to ease concurrent programming. We describe a software transactional memory (STM) system that is part of McRT, an experimental Multi-Core RunTime. The McRT-STM implementation uses a number of novel algorithms, and supports advanced features such as nested transactions with partial aborts, conditional signaling within a transaction, and object based conflict detection for C/C++ applications. The McRT-STM exports interfaces that can be used from C/C++ programs directly or as a target for compilers translating higher level linguistic constructs. We present a detailed performance analysis of various STM design tradeoffs such as pessimistic versus optimistic concurrency, undo logging versus write buffering, and cache line based versus object based conflict detection. We also show a MCAS implementation that works on arbitrary values, coexists with the STM, and can be used as a more efficient form of transactional memory. To provide a baseline we compare the performance of the STM with that of fine-grained and coarse-grained locking using a number of concurrent data structures on a 16-processor SMP system. We also show our STM performance on a non-synthetic workload - the Linux sendmail application. Copyright © 2006 ACM.

关键词： Data storage equipment

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Hunting Trojan Horses

Hunting Trojan Horses

引用

ASID'06: 1st Workshop on Architectural and System Support for Improving Software Dependability

作者： Moffie, Micha Cheng, Winnie Kaeli, David Zhao, Qin Computer Architecture Research Laboratory Northeastern University Boston MA 02115 United States Computer Science and Artificial Intelligence Lab. Massachusetts Institute of Technology Cambridge MA 02139 United States Singapore-MIT Alliance National University of Singapore Singapore 117576 Singapore

ISBN: (纸本)1595935762

HTH (Hunting Trojan Horses) is a security framework developed for detecting difficult types of intrusions. HTH is intended as a complement to anti-virus software in that it targets unknown and zero-day Trojan Horses and Backdoors. In order to accurately identify these types of attacks HTH utilizes runtime information available during execution. The information collected includes fine-grained information flow, program execution flow and resources *** this paper we present Harrier, an Application Security Monitor at the heart of our HTH framework. Harrier is an efficient run-time monitor that dynamically collects execution-related data. Harrier is capable of collecting information across different abstraction levels including architectural, system and library APIs. To date, Harrier is 3-4 times faster than comparable information flow tracking *** the collected information, Harrier allows for accurate identification of abnormal program behavior. Preliminary results show a good detection rate with a low rate of false positives. Copyright 2006 ACM.

关键词： computer software

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Generating different realistic humanoid motion

引用

16th International Conference on Artificial Reality and Telexistence, ICAT 2006

作者： Li, Zhenbo Deng, Yu Li, Hua Key Lab. of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University of Chinese Academy of Sciences Beijing 100039 China

ISBN: (纸本)3540497765

Different realistic humanoid motion can be used in vary situations in animation. It also plays an important role in virtual reality. In this paper, we propose a novel method to generate different realistic humanoid motion automatically. Firstly, eigenvectors of a motion sequence is computed using principle component analysis. The principle components are served as "virtual joints" in our system. The number of "virtual joints" can be used to control the realistic level of motions. After given the "virtual joints" number, the actual joints' parameters of new motion are computed using the selected "virtual joints". The experiments illuminate that this method has good ability to generate different realistic level motions. © 2006 Springer-Verlag Berlin/Heidelberg.

关键词： Principal component analysis

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New architectures for modulo 2N - 1 Adders

New architectures for modulo 2N - 1 Adders

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12th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2005

作者： Dimitrakopoulos, G. Nikolos, D.G. Vergos, H.T. Nikolos, D. Efstathiou, C. Technology and Computer Architecture Lab Computer Engineering and Informatics Dept. University of Patras 26500 Patras Greece Informatics Department ATEI of Athens 12210 Egaleo Athens Greece

ISBN: (纸本)9789972611001

Two architectures for parallel-prefix modulo 2n - 1 adders are presented in this paper. For large wordlengths we introduce the sparse modulo 2n - 1 adders that achieve significant reduction of the wiring complexity without imposing any delay penalty. Then, the Ling-carry formulation of modulo 2n - 1 addition is presented. Ling modulo adders save one logic level of implementation and provide high-speed solutions for smaller adder widths, where wiring complexity is small. The performance of the proposed adders has been validated with static CMOS implementations. In all examined cases, the proposed designs achieve significant savings in both area and delay compared to previously published architectures.

关键词： Adders

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