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IEEE International Symposium on Biomedical Imaging

作者： Zili Kang Yifan Lv Mengshen He Yiheng Liu Tianming Liu Bao Ge School of Physics & Information Technology Shaanxi Normal University Xi’an China Department of Computer Science and Bioimaging Research Center Cortical Architecture Imaging and Discovery Lab The University of Georgia GA USA

It has been of great interest to study relationship between white matter and gray matter in brain science. Previous studies have found that that the formation of gray matter is closely related to white matter. This paper attempts explore the relationship between cerebral cortex and white matter from the perspective of brain image, which tries to predict fiber connection information by using brain cortical information alone. The extensive experiments on HCP dataset demonstrate that brain cortical surface can be used to predict the presence or absence of fibers between any two cortical regions with about 80% accuracy, furtherly, it can be used to predict the fractional anisotropy (FA) value for each fiber, the experiments show that the FA value can be also predicted with a percentage error of about 20%. These results demonstrate that the brain surface can be used to predict fiber connection information, and there is a close relationship between the gray matter and white matter fiber. This work provides a new perspective for further study of the relationship between cerebral cortex and axonal fiber.

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AgileWatts: An Energy-Efficient CPU Core Idle-State architecture for Latency-Sensitive Server Applications 22

AgileWatts: An Energy-Efficient CPU Core Idle-State Architec...

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Proceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture

作者： Jawad Haj Yahya Haris Volos Davide B. Bartolini Georgia Antoniou Jeremie S. Kim Zhe Wang Kleovoulos Kalaitzidis Tom Rollet Zhirui Chen Ye Geng Onur Mutlu Yiannakis Sazeides Rivos Inc Mountain View California United States Computer Architecture Laboratory Department of Computer Science University of Cyprus Computing Systems Lab Huawei Zurich Research Center Department of Information Technology and Electrical Engineering ETH Zurich Switzerland

ISBN: (纸本)9781665462723

User-facing applications running in modern datacenters exhibit irregular request patterns and are implemented using a multitude of services with tight latency requirements (30--250μs). These characteristics render existing energy-conserving techniques ineffective when processors are idle due to the long transition time (order of 100μs) from a deep CPU core idle power state (C-state). While prior works propose management techniques to mitigate this inefficiency, we tackle it at its root with AgileWatts (AW): a new deep CPU core C-state architecture optimized for datacenter server processors targeting latency-sensitive *** drastically reduces the transition latency from deep CPU core idle power states while retaining most of their power savings based on three key ideas. First, AW eliminates the latency (several microseconds) of saving/restoring the core context when powering-off/-on the core in a deep idle state by i) implementing medium-grained power-gates, carefully distributed across the CPU core, and ii) retaining context in the power-ungated domain. Second, AW eliminates the flush latency (several tens of microseconds) of the L1/L2 caches when entering a deep idle state by keeping L1/L2 content power-ungated. A small control logic also remains ungated to serve cache coherence traffic. AW implements cache sleep-mode and leakage reduction for the power-ungated domain by lowering a core's voltage to the minimum operational level. Third, using a state-of-the-art power efficient all-digital phase-locked loop (ADPLL) clock generator, AW keeps the PLL active and locked during the idle state, cutting microseconds of wake-up latency at negligible power *** evaluation with an accurate industrial-grade simulator calibrated against an Intel Skylake server shows that AW reduces the energy consumption of Memcached by up to 71% (35% on average) with <1% end-to-end performance degradation. We observe similar trends for other evaluated services (MySQL and Kafka).

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Co-designing a technology Probe with Experienced Designers 33

Co-designing a Technology Probe with Experienced Designers

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33rd Australian computer-Human Interaction Conference, OzCHI 2021

作者： Gough, Phillip Kocaballi, A. Baki Naqshbandi, Khushnood Z. Cochrane, Karen Mah, Kristina Pillai, Ajit G. Yorulmaz, Yeliz Deny, Ainnoun Kornita Ahmadpour, Naseem Affective Interactions Lab School of Architecture Design and Planning The University of Sydney Australia School of Computer Science University of Technology Sydney Australia School of It Carleton University Canada Independent Artist Australia

ISBN: (纸本)9781450395984

technology probes are low-fidelity devices that can be used to understand research participant's lived experiences, but they are not usually subject to iterative design. There are opportunities in human-computer interaction to develop technology probes through co-design, by including diverse perspectives during probe development. To explore this opportunity, five design researchers with different disciplinary and cultural backgrounds engaged with a technology probe to support daily reflections, discussed new directions in a co-design workshop and developed narratives to negotiate possibilities of the probe. This paper presents observations described by each of the researchers using the probe, and insights from the process we followed. We discuss how the the designers' postitionalities are reflected in the processes, and how they brought value by shaping narratives of the different roles a technology probe might take. We also discuss how we may use co-design of technology probes as a generative method, highlight the importance of open-endedness in the process, and reflect on lessons learned. © 2021 ACM.

关键词： Iterative methods

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Platform Urbanism for Resident Safety: A Real-Time Predictive Microclimate Risk Monitoring and Alert System

SSRN

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SSRN 2025年

作者： Hossain, Sk Tahsin Yigitcanlar, Tan Nguyen, Kien Xu, Yue City 4.0 Lab School of Architecture and Built Environment Queensland University of Technology 2 George Street BrisbaneQLD4000 Australia School of Electrical Engineering and Robotics Queensland University of Technology 2 George Street BrisbaneQLD4000 Australia School of Computer Science Queensland University of Technology 2 George Street BrisbaneQLD4000 Australia

Urban microclimates significantly impact public health, liveability, and emergency preparedness, yet traditional weather alert systems often rely on centralised data that fails to capture the spatial variability of conditions within cities. This study presents an innovative platform that integrates ArcGIS GeoEvent Server with AIoT-driven predictive analytics to deliver hyper-localised weather alerts. The platform’s adaptable design enables the incorporation of location-specific AI/ML-based predictive models and context-aware notifications, tailored to at-risk populations based on their location, health conditions, and disabilities. Featuring three GeoEvent Services and two ArcGIS Notebook Schedules, the system facilitates real-time data ingestion, processing, predictive modelling, and dissemination. A case study in Brisbane, Australia, demonstrates its capacity to address microclimatic variability, revealing significant differences in thermal stress and precipitation patterns across suburbs. Unlike traditional city-wide alerts, the platform provides targeted notifications prioritising vulnerable groups such as children, the elderly, and individuals with chronic conditions or disabilities. This approach enhances urban resilience and offers a scalable framework for applications in health monitoring, emergency response, and public safety. © 2025, The Authors. All rights reserved.

关键词： Emergency services

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Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array

Energy-efficient NTT Design with One-bank SRAM and 2-D PE Ar...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Jianan Mu Huajie Tan Jiawen Wu Haotian Lu Chip-Hong Chang Shuai Chen Shengwen Liang Jing Ye Huawei Li Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences CASTEST Tianjin University Nanyang Technological University Rock-Solid Security Lab Fiberhome

In Number Theoretic Transform (NTT) operation, more than half of the active energy consumption stems from memory accesses. Here, we propose a generalized design method to improve the energy efficiency of NTT operation by considering the effect of processing element (PE) geometry and memory organization on the data flow between PEs and memory. To decrease the number of data bits that are required to be accessed from the memory, a two-dimensional (2-D) PE array architecture is used. A pair of ping-pong buffers are proposed to transposed swap the coefficients to enable a single bank of memory to be used with the 2-D PE array to reduce the average memory bit access energy without compromising the throughput. Our experimental results show that this design method can produce NTT accelerators with up to 69.8% saving in average energy consumption compared with the existing designs based on multi-bank SRAM and one-bank SRAM with one-dimensional PE array with the same number of PEs and total memory size.

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Co-designing a technology Probe with Experienced Designers 21

Co-designing a Technology Probe with Experienced Designers

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Proceedings of the 33rd Australian Conference on Human-computer Interaction

作者： Phillip Gough A. Baki Kocaballi Khushnood Z. Naqshbandi Karen Cochrane Kristina Mah Ajit G. Pillai Yeliz Yorulmaz Ainnoun Kornita Deny Naseem Ahmadpour Affective Interactions Lab School of Architecture Design and Planning The University of Sydney Australia School of Computer Science University of Technology Sydney Australia School of IT Carleton University Canada Affective Interactions Lab The university of Sydney Australia Independent Artist Australia School of Computer Science University of Technology Sydney Australia Affective Interactions lab School of Architecture Design and Planning The University of Sydney Australia

ISBN: (纸本)9781450395984

technology probes are low-fidelity devices that can be used to understand research participant’s lived experiences, but they are not usually subject to iterative design. There are opportunities in human-computer interaction to develop technology probes through co-design, by including diverse perspectives during probe development. To explore this opportunity, five design researchers with different disciplinary and cultural backgrounds engaged with a technology probe to support daily reflections, discussed new directions in a co-design workshop and developed narratives to negotiate possibilities of the probe. This paper presents observations described by each of the researchers using the probe, and insights from the process we followed. We discuss how the the designers’ postitionalities are reflected in the processes, and how they brought value by shaping narratives of the different roles a technology probe might take. We also discuss how we may use co-design of technology probes as a generative method, highlight the importance of open-endedness in the process, and reflect on lessons learned.

关键词： reflection technology probes positionality co-design

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Self-Adjusting Network Slicing for Dynamic Heterogeneous Task Offloading in UAV-Enabled Mobile Edge Computing

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IEEE Transactions on Cognitive Communications and Networking 2025年

作者： Li, Xulong Mao, Wencan Xu, Xinyi Liu, Yaxi Zhang, Huifeng Huangfu, Wei Long, Keping University of Science and Technology Beijing School of Computer and Communication Engineering Beijing100083 China National Institute of Informatics Information Systems Architecture Science Research Division Tokyo101-8430 Japan Zhejiang Lab Hangzhou311500 China

Unmanned aerial vehicle (UAV)-enabled mobile edge computing (MEC) has received wide attention for its ability to significantly reduce latency with flexible mobile aerial nodes. However, the existing works merely consider a fixed periodic network slicing and usually neglect the characterization of computing tasks in practical applications. Motivated by this, we envision a novel scenario where the dynamics and heterogeneity of users and tasks are considered in UAV-enabled MEC networks. We propose a novel self-adjusting two-timescale network slicing scheme based on the internal mechanism in deep reinforcement learning (DRL) to automatically determine whether and when network slicing needs to be reconstructed. Such a novel scheme balances reconstruction cost and system performance compared with traditional fixed schemes. We build an optimization to minimize total system cost for joint UAV trajectory planning and resource allocation at both network and user slice levels. To tackle this problem, we design a novel self-adjusting two-timescale proximal policy optimization (PPO) algorithm that utilizes the property of the critic network, referred to as SaTPPO. Experiment results manifest the effectiveness of the proposed SaTPPO, and it has a lower system cost than the traditional fixed schemes. Moreover, the proposed SaTPPO outperforms the state-of-the-art baselines concerning effectiveness and efficiency. © 2015 IEEE.

关键词： Micro air vehicle (MAV)

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HIORE: Leveraging High-order Interactions for Unified Entity Relation Extraction

arXiv

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arXiv 2023年

作者： Wang, Yijun Sun, Changzhi Wu, Yuanbin Li, Lei Yan, Junchi Zhou, Hao WeChat Technical Architecture Department Tencent Inc China Department of Computer Science and Engineering Shanghai Jiao Tong University China School of Computer Science and Technology East China Normal University China ByteDance AI Lab China University of California Santa Barbara United States

Entity relation extraction consists of two sub-tasks: entity recognition and relation extraction. Existing methods either tackle these two tasks separately or unify them with word-byword interactions. In this paper, we propose HIORE, a new method for unified entity relation extraction. The key insight is to leverage the high-order interactions, i.e., the complex association among word pairs, which contains richer information than the first-order word-by-word interactions. For this purpose, we first devise a W-shape DNN (WNet) to capture coarse-level high-order connections. Then, we build a heuristic high-order graph and further calibrate the representations with a graph neural network (GNN). Experiments on three benchmarks (ACE04, ACE05, SciERC) show that HIORE achieves the state-of-the-art performance on relation extraction and an improvement of 1.1 ∼ 1.8 F1 points over the prior best unified model. Copyright © 2023, The Authors. All rights reserved.

关键词： Graph neural networks

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Mortar: Morphing the Bit Level Sparsity for General Purpose Deep Learning Acceleration

Mortar: Morphing the Bit Level Sparsity for General Purpose ...

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Asia and South Pacific Design Automation Conference

作者： Yunhung Gao Hongyan Li Kevin Zhang Xueru Yu Hang Lu School of Electronics Engineering and Computer Science Peking University Beijing China State Key Lab of Computer Architecture Institute of Computing Technology CAS University of Chinese Academy of Sciences Beijing China Shanghai Integrated Circuits R&D Center Co. Ltd Shanghai China

Vanilla Deep Neural Networks (DNN) after training are represented with native floating-point 32 (fp32) weights. We observe that the bit-level sparsity of these weights is very abundant in the mantissa and can be directly exploited to speed up model inference. In this paper, we propose Mortar, an off-line/on-line collaborated approach for fp32 DNN acceleration, which includes two parts: first, an off-line bit sparsification algorithm to construct the target formulation by “mantissa morphing”, which maintains higher model accuracy while increasing bit-level sparsity; second, the associating hardware accelerator architecture to speed up the on-line fp32 inference through manipulating the enlarged bit sparsity. We highlight the following results by evaluating various deep learning tasks, including image classification, object detection, video understanding, video & image super-resolution, etc.: We (1) increase bit-level sparsity up to 1.28~2.51x with only a negligible -0.09~0.23% accuracy loss, (2) maintain on average 3.55% higher model accuracy while increasing more bit-level sparsity than the baseline, (3)and our hardware accelerator outperforms up to 4.8x over the baseline, with an area of 0.031 mm 2 and power of 68.58mW.

关键词： Deep learning Training Mortar Superresolution Software algorithms Inference algorithms Software

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A differential public PUF design for lightweight authentication 16

A differential public PUF design for lightweight authenticat...

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2021 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2021 and 16th Conference on PhD Research in Microelectronics and Electronics, PRIME 2021

作者： Duan, Shengyu Sai, Gaole School of Computer Engineering and Science Shanghai University Shanghai200444 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China Guangdong Provincial Key Lab of Robotics and Intelligent System Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences China CAS Key Laboratory of Human-Machine Intelligence-Synergy Systems Shenzhen Institutes of Advanced Technology China

ISBN: (纸本)9783800755899

Physical Unclonable Functions (PUFs) have emerged as a promising primitive to provide a hardware keyless security mechanism for integrated circuit applications. Public PUFs (PPUFs) address the crucial PUF vulnerability of requiring databases to store the secrete reference information. This paper investigates one of the PPUF families, differential PPUF (dPPUF), which exploits complexly interacted logic to create time gap between actual execution and simulation, and to prevent simulation attacks. Conventional dPPUFs have high costs. We observe the repressers have large impact on simulation time, but take a great proportion in current dPPUF structure. We thereby present a represser network with specially designed interconnection and shared logic, to maintain a high circuit complexity and to reduce the area cost. We show the proposed dPPUF has similar resilience over simulation attacks as the conventional design. Area cost can be reduced by up to 44%, and thus the proposed design can be used for lightweight authentication. © VDE VERLAG GMBH.

关键词： Authentication

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