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Proceedings of the 4th India Software Engineering Conference

作者： Das, Dipankar Chakrabarti, P.P. Sinha, Purnendu Electrical and Software Architecture Group GM India Science Lab. Bangalore 560066 India Department of Computer Science and Engineering Indian Institute of Technology Kharagpur Kharagpur 721302 India

ISBN: (纸本)9781450305594

While providing correct functionality has been the thrust of most software design efforts, embedded software poses several additional challenges. Among them is designing robust software which can tolerate inaccurate inputs (coming from degraded sensors), failure of software components, and wearing-out of electro-mechanical parts it controls. For this, a design space exploration is performed and several design options are evaluated for their ability to tolerate quality (or accuracy degradation) faults. While a model-based approach enables an early analysis of quality faults, modeling and analyzing the effects of quality faults is a challenge. In this work we propose a quality fault-tolerance analysis framework which is used on operation-level models of embedded software, and an abstraction of quality-faults suitable for this analysis. The proposed method consists of characterizing individual components of the model, and then using the pre-characterized behaviors to quickly evaluate the software design. Characterization is a one-time effort and results of the same can be reused when a new design is evaluated. This results in additional speedup of upto 6-10× faster evaluation of designs, thereby facilitating a quick early evaluation of design options.

关键词： Software design

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Numerical analysis of back berm on road engineering with FEM

Numerical analysis of back berm on road engineering with FEM

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2013 4th International Conference on Material and Manufacturing technology, ICMMT 2013

作者： Liu, Jie Qun Wang, Dong Lin Department of Computer Science and Technology Key Lab of Network and Intelligent Information Processing Hefei University Hefei China School of Civil Engineering Anhui Institute of Architecture and Industry Hefei China

ISBN: (纸本)9783037857526

Based on nonlinear finite element method (FEM), the effect of back berm has been systematically studied. It is found that the lateral displacement of embankment could be reduced by back berm effectively, and the stability of embankment increased rapidly with the width of back berm enlarged. There is a critical value of width of back berm, that the stability of embankment is no more increased with the width of back berm enlarged than critical value. © (2013) Trans Tech Publications, Switzerland.

关键词： Safety factor

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Accurate Congestion Control for RDMA Transfers 18

Accurate Congestion Control for RDMA Transfers

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International Symposium on Networks-on-Chip (NOCS)

作者： Dimitris Giannopoulos Nikos Chrysos Evangelos Mageiropoulos Giannis Vardas Leandros Tzanakis Manolis Katevenis Computer Architecture and VLSI systems Lab Institute of Computer Science Foundation for Research and Technology Hellas

ISBN: (纸本)9781538648933

High-performance interconnects need congestion control to deal with traffic bursts. In this paper, we propose ACCurate, a congestion control protocol that assigns exact max-min fair rates to flows, without relying on costly per-flow state inside the network. ACCurate keeps the backlogs outside of the network, protects innocent flows, and promptly recovers the flows' rates after congestive episodes. Comparisons with TCP and PAUSE-only RDMA under datacenter-resembling workloads further show that ACCurate provides up to 10× faster flow completion times. ACCurate relies on simple hardware that can be readily implemented inside switches. In our implementation, the additional circuitry needed in a 16×16 switch occupies less than 2% of FPGA resources.

关键词： Heart beat Hardware Engines Routing Protocols Kernel computer simulation

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Co-designing a technology Probe with Experienced Designers 33

Co-designing a Technology Probe with Experienced Designers

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33rd Australian computer-Human Interaction Conference, OzCHI 2021

作者： Gough, Phillip Kocaballi, A. Baki Naqshbandi, Khushnood Z. Cochrane, Karen Mah, Kristina Pillai, Ajit G. Yorulmaz, Yeliz Deny, Ainnoun Kornita Ahmadpour, Naseem Affective Interactions Lab School of Architecture Design and Planning The University of Sydney Australia School of Computer Science University of Technology Sydney Australia School of It Carleton University Canada Independent Artist Australia

ISBN: (纸本)9781450395984

technology probes are low-fidelity devices that can be used to understand research participant's lived experiences, but they are not usually subject to iterative design. There are opportunities in human-computer interaction to develop technology probes through co-design, by including diverse perspectives during probe development. To explore this opportunity, five design researchers with different disciplinary and cultural backgrounds engaged with a technology probe to support daily reflections, discussed new directions in a co-design workshop and developed narratives to negotiate possibilities of the probe. This paper presents observations described by each of the researchers using the probe, and insights from the process we followed. We discuss how the the designers' postitionalities are reflected in the processes, and how they brought value by shaping narratives of the different roles a technology probe might take. We also discuss how we may use co-design of technology probes as a generative method, highlight the importance of open-endedness in the process, and reflect on lessons learned. © 2021 ACM.

关键词： Iterative methods

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Classification based scheduling in Heterogeneous ISA architectures

Classification based scheduling in Heterogeneous ISA Archite...

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International Symposium on VLSI Design and Test (VDAT)

作者： Nirmal Kumar Boran Dinesh Kumar Yadav Rishabh Iyer Computer Architecture and Dependable System Lab Indian Institute of Technology Bombay India

ISBN: (数字)9781728193694

ISBN: (纸本)9781728193700

Heterogeneous-ISA multi-core architectures are emerging as promising architectures to enhance single-threaded performance. Multiple cores in such architectures differ in their Instruction Set architectures (ISAs). To achieve maximum performance gain, the program needs to be divided into several phases and each phase should run on its best affine core. Hence, the best affined core for each phase is needed to be known dynamically apriori. In this work, we propose a classification based technique that attempts to classify the phase of the program into the class of core (in terms of microarchitecture and ISA) it is most suited to. This technique leverages several online hardware performance counters to accurately predict the most affine core for each phase. Results show that our classification based predictor achieves single thread performance average speedup of 35.7% with respect to a baseline single ISA heterogeneous architecture.

关键词： Multicore processing Hardware Benchmark testing Parallel processing Scheduling Training

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REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture

REMO: Redundant execution with minimum area, power, performa...

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IEEE Symposium on On-Line Testing (IOLTS)

作者： Shoba Gopalakrishnan Virendra Singh Computer Architecture & Dependable Systems Lab Indian Institute of Technology Bombay India

ISBN: (纸本)9781509015085

Relentless scaling in CMOS fabrication technology has made contemporary integrated circuits continue to evolve and grow in functionality with high clock frequencies and exponentially increasing transistor counts. However, it also makes them more susceptible to transient faults effectively decreasing their reliability. Therefore, ensuring correct and reliable operation of these microprocessors at low cost has become a challenging task. This paper proposes a light weight error detection method called REMO which aims to incorporate simple fault tolerance mechanisms as part of the basic architecture. It dynamically verifies the execution results of the instructions by exploiting spatial and temporal redundancy and detects soft errors. REMO shows that with minimal area, power and performance overhead, and a very low detection latency, a very high degree of fault coverage can be achieved. Our simulation results shows an increase in area is about 0.4%, power overhead near to 9% and a negligible performance penalty during fault free run.

关键词： Redundancy Out of order Pipelines Hardware Fault tolerant systems

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Improving the network energy efficiency in MapReduce systems

Improving the network energy efficiency in MapReduce systems

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2013 IEEE 2013 22nd International Conference on computer Communication and Networks, ICCCN 2013

作者： Wang, Lin Zhang, Fa Liu, Zhiyong Institute of Computing Technology Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Chinese State Key Lab. for Computer Architecture ICT CAS Beijing China

ISBN: (纸本)9781467357746

Apart from servers, the energy consumed by enormous amount of network devices in data centers also emerges as a big problem. Existing work on energy- efficient data center networking primarily focuses on traffic engineering to consolidate flows and shut down unused devices, not considering another important factor, virtual machine assignment, which has been shown to have a big influence on traffic engineering. Moreover, the lack of information about upper layer applications leads to misunderstand the traffic patterns of the network. This may result in poor effectiveness in the traffic-based optimization in practice. In this paper, we aim to achieve better network energy efficiency in MapReduce systems by combining virtual machine assignment and traffic engineering. By exploiting the characteristics of MapReduce applications, we provide a unified model to describe this problem. Due to its NP-hardness, a general framework is proposed to solve it, where virtual machines are first clustered and then different virtual machine assignments are generated greedily and a local search procedure is used to improve them. The local search procedure depends on the results of an energy-efficient routing provided by GEERA. GEERA is an approximate algorithm designed to select routing paths for flows. Experimental results confirm the efficiency of GEERA, as well as the overall framework. By using this framework, up to 20% more energy savings can be achieved compared with sole traffic engineering solutions. © 2013 IEEE.

关键词： MapReduce

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A trace signal selection algorithm for improved post-silicon debug

A trace signal selection algorithm for improved post-silicon...

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East-West Design & Test Symposium (EWDTS)

作者： Binod Kumar Ankit Jindal Virendra Singh Computer Architecture and Dependable Systems Lab (CADSL) Indian Institute of Technology Bombay India

ISBN: (纸本)9781509006946

Enhancing observability is a key challenge in post-silicon validation. On-chip trace buffers store real time data which can be used for analyzing and debugging. Appropriate selection of these signals is crucial for storing useful debug data. This paper proposes a methodology for identifying trace signals so as to maximize detection of erroneous behavior of the failing chip which helps in improving quality of information available for debugging. Different quantitative measures are proposed to assess utility of debug data. Experimental results on benchmark circuits indicate that the methodology is useful for selecting trace signals which maximize debug data effectiveness.

关键词： computer bugs Clocks Logic gates Buffer storage Algorithm design and analysis Silicon Debugging

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NeuroPod: a real-time neuromorphic spiking CPG applied to robotics

arXiv

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arXiv 2019年

作者： Gutierrez-Galan, Daniel Dominguez-Morales, Juan P. Perez-Peña, Fernando Linares-Barranco, Alejandro Robotics and Computer Technology Lab Universidad de Sevilla Spain Department of Computer Architecture and Technology Universidad de Cádiz Spain

Initially, robots were developed with the aim of making our life easier, carrying out repetitive or dangerous tasks for humans. Although they were able to perform these tasks, the latest generation of robots are being designed to take a step further, by performing more complex tasks that have been carried out by smart animals or humans up to date. To this end, inspiration needs to be taken from biological examples. For instance, insects are able to optimally solve complex environment navigation problems, and many researchers have started to mimic how these insects behave. Recent interest in neuromorphic engineering has motivated us to present a real-time, neuromorphic, spike-based Central Pattern Generator of application in neurorobotics, using an arthropod-like robot. A Spiking Neural Network was designed and implemented on SpiNNaker. The network models a complex, online-change capable Central Pattern Generator which generates three gaits for a hexapod robot locomotion. Reconfigurable hardware was used to manage both the motors of the robot and the real-time communication interface with the Spiking Neural Networks. Real-time measurements confirm the simulation results, and locomotion tests show that NeuroPod can perform the gaits without any balance loss or added delay. Copyright © 2019, The Authors. All rights reserved.

关键词： Neural networks

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A channel estimator for OFDM transmitter diversity systems without a cyclic prefix

A channel estimator for OFDM transmitter diversity systems w...

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2003 IEEE International Conference on Accoustics, Speech, and Signal Processing

作者： Lee, King F. Williams, Douglas B. Multimedia Architecture Lab. Motorola Labs Schaumburg IL 60196 United States Sch. of Elec./Computer Engineering Georgia Institute of Technology Atlanta GA 30332-0250 United States

OFDM transmitter diversity systems that do not required a cyclic prefix have recently been proposed as means to improve bandwidth efficiency. For these systems, knowledge of the channel parameters is required at the receivers for interference cancellation, diversity combining, and decoding, In this paper, we propose a low complexity pilot-symbol-assisted channel estimator for OFDM transmitter diversity systems without a cyclic prefix. The pilot symbols are constructed to be periodic within an OFDM symbol interval in order to avoid ISI and ICI and to be non-overlapping in frequency to allow for the simultaneous sounding of the multiple diversity channels. The time-varying channel responses are then tracked by interpolating a set of estimates obtained through periodically transmitted pilot symbols. The effectiveness and limitations of the proposed estimator are verified by computer simulations.

关键词： Orthogonal frequency division multiplexing

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