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1st International Symposium on Benchmarking, Measuring, and Optimization, Bench 2018

作者： Hao, Tianshu Huang, Yunyou Wen, Xu Gao, Wanling Zhang, Fan Zheng, Chen Wang, Lei Ye, Hainan Hwang, Kai Ren, Zujie Zhan, Jianfeng State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Dover DE United States Beijing Academy of Frontier Sciences and Technology Beijing China Chinese University of Hongkong at Shenzhen Shenzhen China Zhejiang Lab Zhejiang China

ISBN: (纸本)9783030328122

In edge computing scenarios, the distribution of data and collaboration of workloads on different layers are serious concerns for performance, privacy, and security issues. So for edge computing benchmarking, we must take an end-to-end view, considering all three layers: client-side devices, edge computing layer, and cloud servers. Unfortunately, the previous work ignores this most important point. This paper presents the BenchCouncil’s coordinated effort on edge AI benchmarks, named Edge AIBench. In total, Edge AIBench models four typical application scenarios: ICU Patient Monitor, Surveillance Camera, Smart Home, and Autonomous Vehicle with the focus on data distribution and workload collaboration on three layers. Edge AIBench is publicly available from http://***/EdgeAIBench/***. We also build an edge computing testbed with a federated learning framework to resolve performance, privacy, and security issues. © 2019, Springer Nature Switzerland AG.

关键词： Edge computing

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The DeSyRe Runtime Support for Fault-Tolerant Embedded MPSoCs

The DeSyRe Runtime Support for Fault-Tolerant Embedded MPSoC...

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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Dionisios Pnevmatikatos Stavros Tzilis Ioannis Sourdis Computer Architecture & VLSI Syst. Lab. Institute of Computer Science Foundation for Research and Technology - Hellas (FORTH) Heraklion- Crete Greece Computer Science and Engineering Dept. Chalmers University of Technology Gothenburg Sweden

Semiconductor technology scaling makes chips more sensitive to faults. This paper describes the DeSyRe design approach and its runtime management for future reliable embedded Multiprocessor Systems-on-Chip (MPSoCs). A light weight runtime system is described for shared-memory MPSoCs to support fault-tolerant execution upon detection of transient and permanent faults. The DeSyRe runtime system offers re-execution of tasks that suffer from transient faults and task-migration in cases where a worker processor is permanently faulty. In addition, a faulty worker can potentially remain usable, increasing systems fault-tolerance. This is achieved using alternative task implementations, which avoid the faulty circuit and are indicated in the application-code via pragma annotations, as well as by repairing a faulty core via hardware reconfiguration. Thereby, the system can be dynamically adapted using one or multiple of the above mechanisms to mitigate faults. The DeSyRe runtime system is evaluated using micro-benchmarks running on a Virtex-6 FPGA MPSoC. Results suggest that our enhance default-tolerant runtime system can successfully and efficiently execute all application tasks under a variety of fault cases.

关键词： Runtime Fault tolerance Fault tolerant systems Transient analysis System-on-chip Circuit faults Hardware

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Optimization of GEMV on Intel AVX processor

International Journal of Database Theory and Application

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International Journal of Database Theory and Application 2016年第2期9卷 47-60页

作者： Liang, Jun Zhang, Yunquan Training Center of Electronic Information Beijing Union University Beijing China State Key Lab of Computer Architecture Institute of Computing Technology CAS Beijing China

To improve the performance of BLAS 2 GEMV subroutine under the latest instruction set, Intel AVX, this paper presents a new approach to analyze the new generation instruction set and enhance the efficiency of current data-oriented math subroutines. The whole optimizing process involves memory access optimization, SIMD optimization and parallel optimization. Also, this paper shows the comparison between the traditional SSE instruction set and the AVX instruction set. Experiments show that the optimized GEMV function has obtained considerable increase on performance. Compared with the Intel MKL, GotoBLAS, ATLAS, this optimized GEMV exceeds these BLAS implementations from 5% to 10%.

关键词： Memory architecture

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A Fast and Compact Invertible Sketch for Network-Wide Heavy Flow Detection

arXiv

引用

arXiv 2019年

作者： Tang, Lu Huang, Qun Lee, Patrick P.C. Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong State Key Lab of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences

Fast detection of heavy flows (e.g., heavy hitters and heavy changers) in massive network traffic is challenging due to the stringent requirements of fast packet processing and limited resource availability. Invertible sketches are summary data structures that can recover heavy flows with small memory footprints and bounded errors, yet existing invertible sketches incur high memory access overhead that leads to performance degradation. We present MV-Sketch, a fast and compact invertible sketch that supports heavy flow detection with small and static memory allocation. MV-Sketch tracks candidate heavy flows inside the sketch data structure via the idea of majority voting, such that it incurs small memory access overhead in both update and query operations, while achieving high detection accuracy. We present theoretical analysis on the memory usage, performance, and accuracy of MV-Sketch in both local and network-wide scenarios. We further show how MV-Sketch can be implemented and deployed on P4-based programmable switches subject to hardware deployment constraints. We conduct evaluation in both software and hardware environments. Trace-driven evaluation in software shows that MV-Sketch achieves higher accuracy than existing invertible sketches, with up to 3.38× throughput gain. We also show how to boost the performance of MV-Sketch with SIMD instructions. Furthermore, we evaluate MV-Sketch on a Barefoot Tofino switch and show how MV-Sketch achieves line-rate measurement with limited hardware resource overhead. Copyright © 2019, The Authors. All rights reserved.

关键词： Memory architecture

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Decoding surface code with a distributed neural network based decoder

arXiv

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arXiv 2019年

作者： Varsamopoulos, Savvas Bertels, Koen Almudever, Carmen G. Quantum Computer Architecture Lab Delft University of Technology QuTech Delft University of Technology P.O. Box 5046 Delft2600 GA Netherlands

There has been a rise in decoding quantum error correction codes with neural network based decoders, due to the good decoding performance achieved and adaptability to any noise model. However, the main challenge is scalability to larger code distances due to an exponential increase of the error syndrome space. Note that, successfully decoding the surface code under realistic noise assumptions will limit the size of the code to less than 100 qubits with current neural network based decoders. Such a problem can be tackled by a distributed way of decoding, similar to the Renormalization Group (RG) decoders. In this paper, we introduce a decoding algorithm that combines the concept of RG decoding and neural network based decoders. We tested the decoding performance under depolarizing noise with noiseless error syndrome measurements for the rotated surface code and compared against the Blossom algorithm and a neural network based decoder. We show that similar level of decoding performance can be achieved between all tested decoders while providing a solution to the scalability issues of neural network based decoders. Copyright © 2019, The Authors. All rights reserved.

关键词： Decoding

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Point-Correlate Adversarial Transformer for Unsupervised Multivariate Time Series Anomaly Detection

Point-Correlate Adversarial Transformer for Unsupervised Mul...

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International Conference on computer Supported Cooperative Work in Design

作者： Huan Li Xiangjie Kong Guojiang Shen Xiaoran Yan Yao Yang Mario Collotta School of Computer Science and Technology Zhejiang University of Technology Hangzhou China Zhejiang Lab Hangzhou China Faculty of Engineering and Architecture Kore University of Enna Enna Italy

ISBN: (数字)9798350349184

ISBN: (纸本)9798350349191

Multivariate time series anomaly detection plays a crucial role in industrial production. However, the inherent complexity and randomness of time series pose significant challenges. Furthermore, existing detection methods struggle to provide reliable explanations for outliers. To address these issues, this paper presents an unsupervised multivariate time series anomaly detection model named Point-Correlate Adversarial Transformer (PCAT). In this work, we leverage Transformer networks to capture the underlying correlations between different points in a time series and reconstruct the original sequence. By analyzing the correlation differences and reconstruction errors, we identify anomalies at the point level. Our model incorporates an adversarial structure, enabling unsupervised learning and enhancing the learning capability and robustness of the detection network. Experimental evaluations on four real-world datasets demonstrate the superiority of our approach over other state-of-the-art models in terms of detection delay and accuracy.

关键词： Training Correlation Accuracy Federated learning Time series analysis Production Transformers

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Identifying Hierarchical Individual Functional Network under Naturalistic Paradigm via Two-stage DBN with Neural architecture Search 4

Identifying Hierarchical Individual Functional Network under...

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4th International Symposium on Image Computing and Digital Medicine, ISICDM 2020

作者： Tao, Zeyang Ren, Yudan Zhang, Wei Liu, Tianming School of Information Science AND Technology Northwest University Xi'an China Department of Radiology and Biomedical Imaging University of California San FranciscoCA United States Cortical Architecture Imaging and Discovery Lab Department of Computer Science and Bioimaging Research Center The University of Georgia AthensGA United States

ISBN: (纸本)9781450389686

Functional magnetic resonance imaging under naturalistic paradigm (NfMRI) is gaining increasing attraction, as it offers an ecologically-valid condition to understand brain function in real life. Characterizing the hierarchical organization of brain function while taking the nature of fMRI activities under naturalistic condition into account has been a critical issue in identifying naturalistic functional networks. Recent studies have made efforts on characterizing the brain's hierarchical organizations from fMRI data via a variety of deep learning models. However, most of those models have ignored the properties of group-wise consistency and inter-subject difference in brain function under naturalistic paradigm. Another critical issue is how to determine the optimal neural architecture of deep learning models, as manual design of neural architecture is time-consuming and less reliable. To tackle these problems, we proposed a two-stage deep belief network (DBN) with neural architecture search (NAS) combined framework (two-stage NAS-DBN framework) to model both the group-consistent and individual-specific naturalistic functional brain networks. Our results demonstrated that the optimized DBN-based framework can characterize meaningful group-wise and individual-level naturalistic functional networks, which reflected the hierarchical organization of brain function and the properties of brain functional activities under naturalistic paradigm. © 2020 ACM.

关键词： Brain

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A computer-supported collaborative learning platform based on clouds

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Journal of Computational Information Systems 2011年第11期7卷 3811-3818页

作者： Li, Jiandun Peng, Junjie Zhang, Wu Han, Fangfang Yuan, Qin Joint Lab of Cloud Computing School of Computer Engineering and Science Shanghai University Shanghai 200072 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

computer-supported collaborative learning (CSCL) is an emerging branch of learning science concerned with studying how people can learn together with the help of computers. As an indispensable ingredient, computer mediation evolves through couples of phases, e.g. centralized server, peer-to-peer network, grid computing. Nevertheless, with daily rising trend on requirement's dynamic changes in service, existing models fall short to respond on demand. Thus, in this paper, by taking advantage of cloud computing, we propose a feasible CSCL platform and the experiments show that it can not only fulfill the basic requirement of CSCL, but also respond to learner's dynamic need on demand. Copyright © 2011 Binary Information Press.

关键词： Peer to peer networks

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YaSpMV: Yet another SpMV framework on GPUs 14

YaSpMV: Yet another SpMV framework on GPUs

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Proceedings of the 19th ACM SIGPLAN symposium on Principles and practice of parallel programming

作者： Yan, Shengen Li, Chao Zhang, Yunquan Zhou, Huiyang Institute of Software Chinese Academy of Sciences University of Chinese Academy of Sciences Beijing China North Carolina State University RaleighNC United States State Key Lab of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Institute of Software Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450326568

SpMV is a key linear algebra algorithm and has been widely used in many important application domains. As a result, numerous attempts have been made to optimize SpMV on GPUs to leverage their massive computational throughput. Although the previous work has shown impressive progress, load imbalance and high memory bandwidth remain the critical performance bottlenecks for SpMV. In this paper, we present our novel solutions to these problems. First, we devise a new SpMV format, called blocked compressed common coordinate (BCCOO), which uses bit flags to store the row indices in a blocked common coordinate (COO) format so as to alleviate the bandwidth problem. We further improve this format by partitioning the matrix into vertical slices to enhance the cache hit rates when accessing the vector to be multiplied. Second, we revisit the segmented scan approach for SpMV to address the load imbalance problem. We propose a highly efficient matrix-based segmented sum/scan for SpMV and further improve it by eliminating global synchronization. Then, we introduce an auto-tuning framework to choose optimization parameters based on the characteristics of input sparse matrices and target hardware platforms. Our experimental results on GTX680 GPUs and GTX480 GPUs show that our proposed framework achieves significant performance improvement over the vendor tuned CUSPARSE V5.0 (up to 229% and 65% on average on GTX680 GPUs, up to 150% and 42% on average on GTX480 GPUs) and some most recently proposed schemes (e.g., up to 195% and 70% on average over clSpMV on GTX680 GPUs, up to 162% and 40% on average over clSpMV on GTX480 GPUs). Copyright © 2014 ACM.

关键词： Graphics processing unit

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Accurate, scalable and informative design space exploration for large and sophisticated multi-core oriented architectures

Accurate, scalable and informative design space exploration ...

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International Symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Chang-Burm Cho James Poe Tao Li Jingling Yuan Intelligent Design of Efficient Architecture Lab IDEAL Department of ECE University of Florida Gainesville FL USA Computer Science and Technology School Wuhan University of Technology Wuhan China

ISBN: (纸本)9781424449279

As microprocessors become more complex, early design space exploration plays an essential role in reducing the time to market and post-silicon surprises. The trend toward multi-/many- core processors will result in sophisticated large-scale architecture substrates (e.g. non-uniformly accessed caches interconnected by network-on-chip) that exhibit increasingly complex and heterogeneous behavior. While conventional analytical modeling techniques can be used to efficiently explore the characteristics (e.g. IPC and power) of monolithic architecture design, existing methods lack the ability to accurately and informatively forecast the complex behavior of large and distributed architecture substrates across the design space. This limitation will only be exacerbated with the rapidly increased integration scale (e.g. number of cores per chip). In this paper, we propose novel, multi-scale 2D predictive models which can efficiently reason the characteristics of large and sophisticated multi-core oriented architectures during the design space exploration stage without using detailed cycle-level simulations. Our proposed techniques employ 2D wavelet multiresolution analysis and neural network regression modeling. We extensively evaluate the efficiency of our predictive models in forecasting the complex and heterogeneous characteristics of large and distributed shared cache interconnected by a network on chip in multi-core designs using both multi-programmed and multithreaded workloads. Experimental results show that the models achieve high accuracy while maintaining low complexity and computation overhead. Through case studies, we demonstrate that the proposed techniques can be used to informatively explore and accurately evaluate global, cooperative multi-core resource allocation and thermal-aware designs that cannot be achieved using conventional design exploration methods.

关键词： Space exploration Predictive models Network-on-a-chip Design methodology Microprocessors Time to market Large-scale systems Analytical models Wavelet analysis Multiresolution analysis

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