Sensitivity to local density effects in both products and scribe line macros is increasing in newer technologies. This can result in significant yield loss at product test because the product measurement structures do...
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Sensitivity to local density effects in both products and scribe line macros is increasing in newer technologies. This can result in significant yield loss at product test because the product measurement structures do not match manufacturing scribe line disposition expectations. A novel strategy to mitigate this problem has been developed and implemented on 32nm ibm ASIC products. Conventional scribe line macro measurements are combined with measurement of macros in each product chip and measurement of the same macros in the scribe line. Four performance screen ring oscillators (PSROs) macros and 28 smaller ring oscillator macros are included in the design of each product. Identical product-like structures are inserted in the scribe line area. Measurements of the macros in the product are compared to the same macros in the scribe line. Measurement differences can be correlated to conventional scribe line macros. This information is used to qualify library elements used in a design system and to center manufacturing lines to optimize yield.
This paper presents a method using only the rank of the measurements to separate a part's elevated response to parametric tests from its non-elevated response. The effectiveness of the proposed method is verified ...
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ISBN:
(纸本)9781424448685
This paper presents a method using only the rank of the measurements to separate a part's elevated response to parametric tests from its non-elevated response. The effectiveness of the proposed method is verified on the 130nm ASIC. Good die responses are correlated for same parametric tests at different conditions such as temperature, voltage and or other stress. Nonparametric correlation methods are used to calculate the intra-die correlation. When intra-die correlation is found to be low the elevated vectors that lower correlation are extracted and input to IDDQ-based diagnostic tools. Monte-Carlo simulations are described to obtain confidence bounds of the correlation for good die test response.
An innovative in-situ electronic package assembly process is presented using the on-chip power to cure the package thermal interface and seal materials and to verify the thermal performance of the electronic package. ...
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ISBN:
(纸本)9781424417001
An innovative in-situ electronic package assembly process is presented using the on-chip power to cure the package thermal interface and seal materials and to verify the thermal performance of the electronic package. The in-situ curing process was thermally modeled to demonstrate that the thermal interface and seal materials would reach their required curing temperatures by controlling the chip power and heat sink air flow. Experimental validation of the in-situ cure method was conducted using thermal test vehicles. Thermal resistance characterization of the in-situ cured package in comparison to a batch oven cured package showed better thermal performance stability with increasing temperature.
An innovative in-situ electronic package assembly process is presented using the on-chip power to cure the package thermal interface and seal materials and to verify the thermal performance of the electronic package. ...
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An innovative in-situ electronic package assembly process is presented using the on-chip power to cure the package thermal interface and seal materials and to verify the thermal performance of the electronic package. The in-situ curing process was thermally modeled to demonstrate that the thermal interface and seal materials would reach their required curing temperatures by controlling the chip power and heat sink air flow. Experimental validation of the in-situ cure method was conducted using thermal test vehicles. Thermal resistance characterization of the in-situ cured package in comparison to a batch oven cured package showed better thermal performance stability with increasing temperature.
INTRODUCTION Maintaining the integrity of the heat dissipation path for high end microelectronic devices has become increasingly challenging as the industry migrates from ceramic to organic packaging. Typically, flip ...
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INTRODUCTION Maintaining the integrity of the heat dissipation path for high end microelectronic devices has become increasingly challenging as the industry migrates from ceramic to organic packaging. Typically, flip chip organic packages undergo significant thermal and mechanical stresses throughout the manufacturing process, including chip join, underfill, encapsulation, BGA attach and card join. As a result of the mismatch of thermal and mechanical properties between the components, significant warpage is generated in the organic substrate, the chip, and the thermal interface material (TIM1) on completion of the assembly. Warpage affects not only the substrate coplanarity but also the thermal performance of the TIM1. At room temperature, the center of an adhesive TIM1 is under compression between the lid and chip while the corners and edges are under tensile stress. The effective thermal conductivity for the portions of the TIM1 under tensile stress can be significantly lower due to the elongation of the gap and the narrowing of the heat flow area. The present paper describes an approach to model the thermal performance of an adhesive thermal interface material taking into account the warpage effects and the inherent out-of-flatness in the heat spreader. Reasonable agreement is obtained between the modeling results and thermal measurements for a representative thermal test vehicle. The present modeling approach can potentially be used to optimize the component design and the bond and assembly process to achieve optimum thermal performance.
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