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cMat 2025年第1期2卷

作者： Zi-Long Xue Qian Li Kai Wang Kai-Rui Chen Qi Zhao Cai-Xia Xu Bin-Bin Liu Institute for Advanced Interdisciplinary Research (IAIR) School of Chemistry and Chemical Engineering University of Jinan Jinan China Institute of Electrical Engineering Chinese Academy of Sciences Beijing China Department of Materials Science and Engineering National University of Singapore Singapore Singapore School of Microelectronics and Integrated Circuits (Jiangsu Key Laboratory of Semi. Dev. & IC Design Package and Test) Nantong University Nantong China

Supercapacitors attracted great attention for their expeditious charge and discharge rates and splendid cyclic stability. The doping of heteroatoms into graphene (G) can alter the electronic configuration of carbon atoms, alleviating the stacking problem of G-based materials. This work focused on a one-step green scalable electrochemical exfoliation strategy for the rapid preparation of high-quality thin-layer G nanosheets with double halogen doping. The as-made chlorine (Cl) and bromine (Br) dual-doped graphene (Cl/Br-G) nanosheets exhibited a transparent feature with a large lateral size. Density functional theoretical calculations indicated that the introduction of Cl and Br can not only enlarge the interlayer spacing of graphene but also produce the charge distribution through the formation of delocalized π bonds in the defect region. The flexible micro-supercapacitor (MSC) constructed with Cl/Br-G as the electrodes demonstrated remarkable charge storage performance and impressive mechanical flexibility. In particular, the Cl/Br-G-MSC displayed much higher specific capacitance and long-term cycling stability for 300,000 cycles compared with the single-doping counterparts. This innovative approach to dual halogen doping in G holds significant promise for energy storage, and the electrochemical exfoliation technique offers valuable insights for producing other two-dimensional layered materials.

关键词： dual-doping energy storage flexible graphene supercapacitors

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26th Annual Computational Neuroscience Meeting (CNS*2017): Part 1

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BMC Neurosci 2017年第SUPPL 1期18卷 58-58页

作者： Sue Denham Panayiota Poirazi Erik De Schutter Karl Friston Ho Ka Chan Thomas Nowotny Dongqi Han Sungho Hong Sophie Rosay Tanja Wernle Alessandro Treves Sarah Goethals Romain Brette Tomas Van Pottelbergh Rodolphe Sepulchre Alex D. Bird Hermann Cuntz Pedro J. Gonçalves Jan-Matthis Lueckmann Giacomo Bassetto Marcel Nonnenmacher Jakob H. Macke Audrey J. Sederberg Jason N. MacLean Stephanie E. Palmer Ulisse Ferrari Christophe Gardella Olivier Marre Thierry Mora Emina Ibrahimovic Martin Müller Jean-Pascal Pfister Tushar Chauhan Timothée Masquelier Alexandre Montlibert Benoit R. Cottereau Moritz Helias Jannis Schuecker David Dahmen Sven Goedeke Alexandre Hyafil Ainhoa Hermoso-Mendizabal Pavel E. Rueda-Orozco Santiago Jaramillo David Robbe Jaime de la Rocha Marie Rooy Fani Koukouli David DiGregorio Uwe Maskos Boris Gutkin Andrey Yu Verisokin Darya V. Verveyko Dmitry E. Postnov Willy Wong Omid Talakoub Robert Chen Milos Popovic Dmitriy Lisitsyn Eric Drebitz Iris Grothe Sunita Mandon Andreas Kreiter Udo Ernst Peter A. Robinson Xuelong Zhao Kevin M. Aquino John D. Griffiths Grishma Mehta-Pandejee Natasha Gabay James MacLaurin Somwrita Sarkar Tim Kunze Jens Haueisen Thomas R. Knösche Subutai Ahmad Yuwei Cui Marcus Lewis Jeff Hawkins Simona Olmi Spase Petkoski Fabrice Bartolomei Maxime Guye Viktor Jirsa Hazem Toutounji Daniel Durstewitz Matteo Cantarelli Adrian Quintana Boris Marin Matt Earnshaw Padraig Gleeson Robert Court Robert McDougal R. Angus Silver Salvador Dura-Bernal Stephen Larson William W. Lytton Giovanni Idili Lorenzo Posani Simona Cocco Karel Ježek Rémi Monasson School of Psychology Faculty of Health & Human Sciences Plymouth University Plymouth Devon PL4 8AA UK Institute of Molecular Biology and Biotechnology (IMBB) Foundation for Research and Technology-Hellas (FORTH) Heraklion Crete Greece Okinawa Institute of Science and Technology Graduate University Okinawa Japan Wellcome Trust Centre for Neuroimaging Institute of Neurology UCL London WC1N 3BG UK School of Engineering and Informatics University of Sussex Brighton BN1 9QJ UK Graduate School Okinawa Institute of Science and Technology Okinawa 904-0495 Japan Computational Neuroscience Unit Okinawa Institute of Science and Technology Okinawa 904-0495 Japan Cognitive Neuroscience Area Scuola Internazionale Superiore di Studi Avanzati Trieste 34136 Italy Kavli Institute for Systems Neuroscience NTNU Trondheim 7030 Norway Institut de la Vision Sorbonne Universités UPMC Univ Paris 06 INSERM CNRS Paris 75012 France Department of Engineering University of Cambridge Cambridge Cambridgeshire CB2 1PZ UK Ernst Strüngmann Institute for Neuroscience Max Planck Society Frankfurt Germany Frankfurt Institute for Advanced Studies Frankfurt Germany Neural Systems Analysis Research Center Caesar An Associate of the Max Planck Society Bonn Germany Max Planck Institute for Biological Cybernetics Tübingen Germany Bernstein Center for Computational Neuroscience Tübingen Germany Present Address: Biomedical Engineering Department Georgia Institute of Technology Atlanta GA 30306 USA Department of Neurobiology University of Chicago Chicago IL 60637 USA Department of Organismal Biology and Anatomy University of Chicago Chicago IL 60637 USA Committee on Computational Neuroscience University of Chicago Chicago IL 60637 USA Institut de la Vision Sorbonne Universités INSERM Paris France Laboratoire de Physique Statistique Ecole Normale Supérieure Paris France Institute of Molecular Life Sciences University of Zürich 8057 Zürich Switzerland Institute of Neuroinformatics Univer

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PARALLEL AND DISTRIBUTED TLM COMPUTATION WITH SIGNAL-PROCESSING FOR ELECTROMAGNETic-FIELD MODELING

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INTERNATIONAL JOURNAL OF NUMERicAL MODELLING-ELECTRONic NETWORKS DEVicES AND FIELDS 1995年第3-4期8卷 169-185页

作者： SO, PPM ESWARAPPA, C HOEFER, WJR NSERC/MPR Teltech Research Chair in RF Engineering Department of Electrical and Computer Engineering University of Victoria Victoria British Columbia V8W 3P6 Canada Poman So received his B.Sc. degree in computer science and physics from the University of Toronto Toronto Onatario Canada in 1985. He obtained his B.A. Sc. and M.A.Sc. degrees in electrical engineering (summa cum laude) from the University of Ottawa Ottawa Ontario Canada in 1987 and 1989 respectively. Mr So was a research engineer in the University of Ottawa from January 1989 to October 1991 his research interests included CAD techniques of microwave circuits and numerical methods for electromagnetic wave modelling. He specialized in the development of electromagnetic engineering CAD software and successfully implemented a number of electromagnetic wave simulators based on the two-dimensional and three-dimensional transmission-line matrix methods. From August 1990 to February 1991 he accompanied Professor W. J. R. Hoefer to Rome Italy and Sophia Antiopolas France. During that time he implemented a parallel version of the 3D-TLM simulator for the CM-2 Connection Machine using C-Star and X Windows Library. He is a research engineer and a Ph.D. student at the University of Victoria Victoria British Columbia Canada. He ported the 2D- and 3D-TLM simulators to DECmpp 1200 massively parallel computer using MPL C and C++. He also combined OSA90/hope a commercially available microwave CAD program with a 2D-TLM simulation module for geometry optimization using the Datapipe technique of OSA90/hope. Recently he has developed a distributed client-server computing technique for the TLM method this technique could accelerate the TLM simulation by more than an order of magnitude. Channabasappa Eswarappa received the M.Tech. degree in electrical engineering from the Indian Institute of Technology Kanpur India in 1983 and Ph. D. degree from the University of Ottawa Canada in 1990. He worked as an Assistant Executive Engineer and later as

This paper describes the implementation of transmission-line matrix (TLM) method algorithms on a massively parallel computer (DECmpp 12000), the technique of distributed computing in the UNIX environment, and the combination of TLM analysis with Prony's method as well as with autoregressive moving average (ARMA) digital signal processing for electromagnetic field modelling. By combining these advanced computation techniques, typical electromagnetic field modelling of microwave structures by TLM analysis can be accelerated by a few orders of magnitude.

关键词： Mathematical models

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Improved lower bounds for the scheduling optimization problem

Improved lower bounds for the scheduling optimization proble...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Yuan Hu B.S. Carlson Electrical Engineering The Advanced IC Design and Simulation Laboratory Stony Brook NY USA

In this paper lower bounds for the performance constrained and resource constrained scheduling of tasks on multiprocessors are presented. The lower bounds derived here are sharper than previously known results and the... 详细信息

关键词： Processor scheduling Constraint optimization design optimization Time measurement Integrated circuit modeling Laboratories Time sharing computer systems Tree graphs Upper bound NP-complete problem

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A unified algorithm for estimation and scheduling in data path synthesis

A unified algorithm for estimation and scheduling in data pa...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Y. Hu B.S. Carlson The Advanced IC Design and Simulation Laboratory and the Department of Electrical Engineering State University of New York Stony Brook NY USA

A unified algorithm is presented to solve the problem of estimation and scheduling for performance constrained data path synthesis. The algorithm achieves superior results by first computing a lower bound on the number of functional units required to satisfy the performance constraint T, and then scheduling the operations into the best control steps using the lower bound algorithm. The lower bound not only greatly reduces the size of the solution space, but also provides a means to measure the proximity of the final solution to an optimal one. Our unified algorithm can also be incorporated in a branch-and-bound algorithm to solve the scheduling problem optimally. Experiments indicate that our scheduling algorithm can produce results very close to the lower bound. For all of the test cases the difference between our upper and lower bounds is not greater than one.< >

关键词： Scheduling algorithm Processor scheduling Flow graphs Testing Upper bound State estimation Algorithm design and analysis Integrated circuit synthesis Computational modeling Integrated circuit modeling

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TECHNicAL ISSUES REGARDING SATELLITE PACKET-SWITCHING

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INTERNATIONAL JOURNAL OF SATELLITE COMMUNicATIONS 1994年第3期12卷 257-267页

作者： IVANCic, WD CHU, P SHYY, DJ National Aeronautics and Space Administration Lewis Research Center Cleveland Ohio 44135 USA. A design engineer in the Digital Technology Branch of the Space Electronics Division. He has extensive experience in satellite communications systems modulation and coding on-board switching and routeing and high speed digital design. Since joining NASA in 1982 Mr. Ivancic has been responsible for the development of a variety of matrix switch controllers ground terminal equipment numerous pieces of special test equipment a beacon controller for the SARSAT program (Search and Rescue Satellite) and a time-shared decoder for a processing satellite. In addition Mr. Ivancic has been technical contract monitor on a number of advanced communications technology contracts including the Advanced Modulation Technology Development a 5 GHz fibre-optic link and multi-programmable modem study. He was awarded the B.S.E.E. and M.S.E.E. degrees by Cleveland State University in 1982 and 1986 respectively. Cleveland State University Cleveland Ohio 44115 USA. Currently an assistant professor of Electrical Engineering Department at Cleveland State University. He obtained the M.S. and Ph.D. degrees from Iowa State University majoring in Electrical and Computer Engineering. His research interests include high-speed computer networks digital systems and neural networks applications. He is a member of Sigma Xi Phi Kappa Phi as well as the IEEE and ACM. ComSearch Reston Virginia 22091 USA. Received the B.S. degree in electrical engineering from National Chiao-Tung University Hsin-Chu Taiwan in 1983 and the M.S. and Ph.D. degrees in electrical engineering from Georgia Institute of Technology Atlanta GA in 1986 and 1990 respectively. From June 1987 to October 1987 he worked for the Department of Neurology Emory University Atlanta as a Programmer. From September 1989 to December 1989 he worked for the Advanced Development Laboratory. AMP Inc. Atlanta as a Test Engineer. From February 1990 to August 1993 he wor

Many concepts for advanced communication satellite networks have recently been proposed. Critical technical issues relating to satellite packet switching for meshed very small aperture terminal networks and broadband ... 详细信息

关键词： FAST PACKET SWITCH BISDN MESHED VSAT ON-BOARD PROCESSING

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HYBRID SATELLITE AND TERRESTRIAL NETWORKS

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INTERNATIONAL JOURNAL OF SATELLITE COMMUNicATIONS 1994年第3期12卷 313-327页

作者： CHITRE, DM SHYY, DJ EPHREMIDES, A GUPTA, S COMSAT Laboratories 22300 Comsat Drive Clarksburg MD 20871–9475 USA. Received his B.Sc. from the University of Bombay India an M.A. in mathematics from the University of Cambridge U.K. and a Ph.D. in physics from the University of Maryland. He is currently an Associate Executive Director of the Network Technology Division at COMSAT Laboratories. He has been involved in research and development activities in ISDN VSAT networks data communications and network systems and architectures. Prior to his current positions Dr. Chitre was a Principal Scientist in the Network Technology Division at COMSAT Laboratories. Dr. Chitre joined COMSAT Laboratories in 1980. He has made major contributions to the analysis and architecture of data communication ISDN and BISDN via satellite. Dr. Chitre directs and participates in the international and national standards activities in ISDN BISDN and data communication as they apply to satellite communication. He was Chairman of the Working Group on Protocols and Network Timing Function of the CCIR/CCITT Joint Ad Hoc Group on ISDN/Satellite Matters during 1990–1992. Currently he is the Chairman of the Working Group on New Technologies in the ITU Intersector Coordinating Group (ICG) on Satellite Matters. Dr. Chitre was a programme manager during 1990 and 1991 on a contract from INTELSAT on systems studies on satellite communications systems architectures for ISDN and broadband ISDN systems. Currently he is the technical manager of the DoD Contract on ATM via satellite demonstration and the programme manager for the INTELSAT contract on analysis and top-level specification of INTELSAT ISDN subnetworks and SDH compatible transport network. Received the B.S. degree in electrical engineering from national Chiao-Tung University Hsin-Chu Taiwan in 1983 and the M.S. and Ph.D. degrees in electrical engineering from Georgia Institute of Technology Atlanta GA in 1986 and 1990 respectively. From June 1987 to October 1987 he worked for the Department of Neurology Emory Univers

The role of satellite communications in networks that provide new services, such as frame relay and multimedia, is investigated. Both passive and active (on-board switching/processing) satellite systems are considered. Novel techniques are developed for each system to demonstrate, via detailed analysis and simulation, how the communications bandwidth agility of multipoint/broadcast satellite channels, and the on-board switching/processing, makes it feasible to provide these new services via hybrid satellite and terrestrial networks in a resource-efficient manner.

关键词： HYBRID NETWORKS ON-BOARD PROCESSING FRAME RELAY

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Lower bounds on the iteration time and the number of resources for functional pipelined data flow graphs

Lower bounds on the iteration time and the number of resourc...

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IEEE International Conference on Computer design: VLSI in Computers and Processors, (icCD)

作者： Y. Hu A. Ghouse B.S. Carlson The Advanced IC Design and Simulation Laboratory and the Department of Electrical Engineering State University of New York Stony Brook NY USA

An algorithm is presented to determine two lower bounds in functional pipelined data path synthesis. Given an iteration time constraint and a task initiation latency, the algorithm computes a lower bound on the number of functional units required to execute the data flow graph (DFG) of a loop body, and given a resource constraint and a task initiation latency the algorithm computes a lower bound on the number of time steps required to execute the DFG. The lower bounds not only greatly reduce the size of the solution space, but also provide a means to measure the proximity of the final solution to an optimal one. The bounds are computed in polynomial time; therefore the algorithm is very effective, especially for large DFGs. Experiments indicate that the lower bound is very tight. For all of the test cases the difference between our solution and the optimal solution is not greater than one.< >

关键词： Flow graphs Data flow computing Scheduling algorithm Optimal scheduling Integrated circuit synthesis Polynomials Pipeline processing Time factors Delay Algorithm design and analysis

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Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering

Performance Enhancement of CMOS VLSI Circuits by Transistor ...

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design Automation Conference

作者： B.S. Carlson C.Y.R. Chen The Advanced IC Design of and Simulation Laboratory and the Department of Electrical Engineering State University of New York Stony Brook NY USA Department of Electrical and Computer Engineering Syracuse University Syracuse NY USA

A method which uses transistor reordering for the performance enhancement of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect on layout area. The technique can be coupled with transistor sizing to achieve unbounded improvement in circuit delay, and it can be used to decrease dynamic power dissipation. In particular, excellent results have been achieved when the method is applied to data path circuits.

关键词： Very large scale integration Propagation delay Transistors Switches Switching circuits Logic gates CMOS logic circuits Logic devices Registers Delay effects

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