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arXiv 2024年

作者： Rogenmoser, Michael Wiese, Philip Forlin, Bruno Endres Gürkaynak, Frank K. Rech, Paolo Menicucci, Alessandra Ottavi, Marco Benini, Luca The Integrated Systems Laboratory ETH Zurich Switzerland The Computer Architecture for Embedded Systems The University of Twente Netherlands The Department of Industrial Engineering The University of Trento Italy The Department of Space Engineering The Delft University of Technology Netherlands The Computer Architecture for Embedded Systems The University of Twente Netherlands The Department of Electronic Engineering The University of Rome Tor Vergata Italy The Integrated Systems Laboratory ETH Zurich Switzerland The Department of Electrical Electronic and Information Engineering The University of Bologna Italy

We present a fault-tolerant by-design RISC-V SoC and experimentally assess it under atmospheric neutrons and 200 MeV protons. The dedicated ECC and Triple-Core Lockstep countermeasures correct most errors, guaranteein... 详细信息

关键词： Fault tolerance

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VersaSens: An Extendable Multimodal Platform for Next-Generation Edge-AI Wearables

IEEE Transactions on Circuits and Systems for Artificial Int...

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IEEE Transactions on Circuits and systems for Artificial Intelligence 2024年第1期1卷 83-96页

作者： Taraneh Aminosharieh Najafi José Angel Miranda Calero Jérôme Thevenot Benjamin Duc Stefano Albini Alireza Amirshahi Hossein Taji María José Belda Beneyto Antonio Affanni David Atienza Embedded Systems Laboratory (ESL) Institute of Electrical and Micro Engineering École Polytechnique Fédérale de Lausanne (EPFL) Lausanne Switzerland Polytechnic Department of Engineering and Architecture Udine Italy Computer Architecture and Automation Department Universidad Complutense de Madrid Madrid Spain

The transition of healthcare towards digitalization is closely related to the advancement of health-related technologies, including wearable sensors and edge computing. In this paper, we present VersaSens, a versatile and customizable platform concept and its real implementation as a tool to boost research in wearable sensors. The platform embodies the core attributes of the VersaSens concept: versatility, flexibility, and extendability across multiple aspects of hardware, software, and processing components. It features a modular design, consisting of sensor, processor, and co-processor modules, allowing for various configurations. To evaluate the efficiency of the platform, we tested three use cases: cough monitoring, heartbeat classification and epileptic seizure detection. In all cases, the results indicate that the platform effectively executes the applications, achieving low energy consumption. In particular, our findings indicates that the integration of a domain-specific edge-AI co-processor [i.e., HEEP ocrates (Machetti et al., 2024)] equipped with several hardware accelerators further improved the overall execution time and energy consumption of the system. These results demonstrate the potential of VersaSens to effectively support a diverse range of edge-AI applications and configurations, thereby providing a robust foundation for the research and development of novel smart wearable sensor systems.

关键词： Sensors Wearable devices Artificial intelligence Wearable sensors Medical services Intelligent sensors Monitoring

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A Clustering-BIST Design for Inter-Layer Vias in 3D ICs Based on Walking Pattern Approach

TechRxiv

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TechRxiv 2023年

作者： Menbari, Ahmad Rahimi, Hemin Jahanirad, Hadi Ziener, Daniel The Department of Electrical Engineering University of Kurdistan Sanandaj Iran The Department of Computer Architecture and Embedded Systems Ilmenau University of Technology Ilmenau Germany

In the realm of 3D monolithic integrated circuits, inter-layer vias are prone to defects during fabrication, assembly, and operation that necessitates robust Built-In Self-Test solutions. This paper introduces an innovative BIST design aimed at the detection and localization of different types of faults in irregularly placed ILVs using a walking pattern methodology. In the proposed BIST methodology, the ILVs are clustered based on the fault occurrence probability distribution. Then, an effective detection approach is developed for all stuck-at faults, bridging faults, and almost all multiple faults in a single cluster. This approach allows designers to adjust different parameters such as fault coverage percentage, fault localization, and test time in alignment with specific requisites. The proposed BIST method reduces test configurations to two and test time to just 20 cycles by dividing ILVs into more clusters, overcoming a key limitation of recent approach. This methodology also demonstrates improved efficiency in terms of power consumption, area, and hardware utilization, particularly for large-scale benchmarks. For instance, when considering LU32PEENG and the scenario where ILVs are divided into 64 clusters, the power, area, and hardware overhead are 0.82% and 1.03%, and 1.14%, respectively. © 2023, CC BY.

关键词： Built-in self test

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EVOAL: A Domain-Specific Language-Based Approach to Optimisation

EVOAL: A Domain-Specific Language-Based Approach to Optimisa...

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Congress on Evolutionary Computation

作者： Bernhard J. Berger Christina Plump Rolf Drechlser Institute of Embedded Systems Hamburg University of Technology Hamburg Germany DFKI GmbH-Cyber-Physical Systems Bremen Germany University Bremen - Computer Architecture Bremen Germany

Adapting optimisation algorithms, such as evolutionary algorithms, to a problem is a necessity. The required collection and exchange of domain information is an important but tedious task in real-world projects involving several experts from different areas of expertise (e.g. the domain and the optimisation area). This paper presents a structured approach that allows the experts to systematically provide their knowledge using domain-specific languages. The presented approach defines a different language for the involved experts that enables them to add their knowledge and use the information provided by other experts. The languages are extensible, allowing the addition of new optimisation aspects without changing the actual language. These languages are the front-end to a versatile open-source optimisation tool, that we built, enabling the actual execution of the optimisation. It additionally provides features for surrogate models as well as data generation and different benchmarks for evaluation. Conducting a user study, we show that the language is suitable to express the domain knowledge and domain experts can use the language to describe their domain knowledge after a short introduction. This way, the approach reduces the effort for domain experts in providing their information. As a side effect, the complete configuration of the optimisation execution through these languages allows an easy and reliable reproduction.

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Unraveling the Mystery of NVIDIA's Unified Memory for Safety-Critical GPU systems

Unraveling the Mystery of NVIDIA's Unified Memory for Safety...

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Euromicro Symposium on Digital System Design

作者： Xabier Arauzo Irune Yarza Leonidas Kosmidis Alejandro J. Calderón Marcos Rodriguez Reliable Embedded Systems Ikerlan Technology Research Centre Computer Architecture Universitat Politècnica de Catalunya Mondragón Spain Reliable Embedded Systems Ikerlan Technology Research Centre Mondragón Spain Computer Architecture Universitat Politècnica de Catalunya Barcelona Super Computing Centre (BSC) Barcelona Spain

In the domain of safety-critical systems there is an increasing need for more compute-capable and higher performance devices. This comes from the dramatic increase on the software complexity caused by the newest intelligent and autonomous systems. Graphics Processing Units (GPUs), as multi-processing accelerators, are an ideal choice in this aspect due to their ability to handle big amount of data and computations. In order to ease the challenging task of programming such devices, vendors are continuously adding features, such as Unified Memory (UM), which allow the programmers to reduce their developing time on GPU applications. However, the use of GPU poses several challenges on safety-critical systems due to its close source nature and proprietary implementation. Therefore, this paper shows a deeper insight on how this feature works and present a way of exploiting this knowledge to reduce the execution time of applications using NVIDIA's UM feature. We demonstrate that these optimizations can make the data migrations predictable and reduce the required time.

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Model Parallelism on Distributed Infrastructure: A Literature Review from Theory to LLM Case-Studies

arXiv

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arXiv 2024年

作者： Brakel, Felix Odyurt, Uraz Varbanescu, Ana-Lucia Informatics Institute University of Amsterdam Amsterdam The Netherlands Vrije Universiteit Amsterdam Amsterdam Netherlands Amsterdam Netherlands Computer Architecture for Embedded Systems University of Twente Enschede The Netherlands Informatics Institute University of Amsterdam Amsterdam Netherlands

Neural networks have become a cornerstone of machine learning. As the trend for these to get more and more complex continues, so does the underlying hardware and software infrastructure for training and deployment. In this survey we answer three research questions: "What types of model parallelism exist?", "What are the challenges of model parallelism?", and "What is a modern use-case of model parallelism?" We answer the first question by looking at how neural networks can be parallelised and expressing these as operator graphs while exploring the available dimensions. The dimensions along which neural networks can be parallelised are intra-operator and inter-operator. We answer the second question by collecting and listing both implementation challenges for the types of parallelism, as well as the problem of optimally partitioning the operator graph. We answer the last question by collecting and listing how parallelism is applied in modern multi-billion parameter transformer networks, to the extend that this is possible with the limited information shared about these networks. © 2024, CC BY.

关键词： Deep learning

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Fault Management Impacts on the Networking systems Hardware Design 49

Fault Management Impacts on the Networking Systems Hardware ...

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49th Annual Conference of the IEEE Industrial Electronics Society, IECON 2023

作者： Vitucci, Carlo Sundmark, Daniel Jagemar, Marcus Danielsson, Jakob Larsson, Alf Nolte, Thomas Ericsson Ab Technology Management Stockholm Sweden Mälardalen University Computer Science and Software Enigineering Vasterås Sweden Ericsson Ab Sys Compute Dimensioning Stockholm Sweden Ericsson Ab Sys Architecture Stockholm Sweden Ericsson Ab Senior Specialist Observability Stockholm Sweden Mälardalen University Networked and Embedded Systems Västerås Sweden

ISBN: (纸本)9798350331820

Processing capacity distribution has become widespread in the fog computing era. End-user services have multiplied, from consumer products to Industry 5.0. In this scenario, the services must have a very high-reliability level. But in a system with such displacement of hardware, the reliability of the service necessarily passes through the hardware design. Devices shall have a high quality, but they shall also efficiently support fault management. Hardware design must take into account all fault management functions and participate in creating a fault management policy to ensure that the ultimate goal of fault management is fulfilled, namely to increase a system's reliability. Efficiently and sustainably, both in the system's performance and the product's cost. This paper analyzes the hardware design techniques that efficiently contribute to the realization of fault management and, consequently, guarantee a high level of reliability and availability for the services offered to the end customer. We describe hardware requirements and how they affect the choice of devices in the hardware design of networking systems. © 2023 IEEE.

关键词： Consumer products

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Novel Approaches for ML-Assisted Particle Track Reconstruction and Hit Clustering

arXiv

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arXiv 2024年

作者： Odyurt, Uraz Dobreva, Nadezhda Wolffs, Zef Zhao, Yue Sánchez, Antonio Ferrer de Austri Bazan, Roberto Ruiz Martín-Guerrero, José D. Varbanescu, Ana-Lucia Caron, Sascha High-Energy Physics department Radboud University Netherlands Netherlands SURF Netherlands Instituto de Física Corpuscular University of Valencia Spain IDAL Department of Electronic Engineering ETSE-UV University of Valencia Spain Spain Computer Architecture for Embedded Systems University of Twente Netherlands

Track reconstruction is a vital aspect of High-Energy Physics (HEP) and plays a critical role in major experiments. In this study, we delve into unexplored avenues for particle track reconstruction and hit clustering. Firstly, we enhance the algorithmic design effort by utilising a simplified simulator (REDVID) to generate training data that is specifically composed for simplicity. We demonstrate the effectiveness of this data in guiding the development of optimal network architectures. Additionally, we investigate the application of image segmentation networks for this task, exploring their potential for accurate track reconstruction. Moreover, we approach the task from a different perspective by treating it as a hit sequence to track sequence translation problem. Specifically, we explore the utilisation of Transformer architectures for tracking purposes. Our preliminary findings are covered in detail. By considering this novel approach, we aim to uncover new insights and potential advancements in track reconstruction. This research sheds light on previously unexplored methods and provides valuable insights for the field of particle track reconstruction and hit clustering in HEP. © 2024, CC BY.

关键词： High energy physics

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Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC

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IEEE Transactions on Nuclear Science 2025年

作者： Rogenmoser, Michael Wiese, Philip Forlin, Bruno Endres Gurkaynak, Frank K. Rech, Paolo Menicucci, Alessandra Ottavi, Marco Benini, Luca Integrated Systems Laboratory ETH Zurich Switzerland Computer Architecture for Embedded Systems University of Twente Netherlands Department of Industrial Engineering University of Trento Italy Delft University of Technology Department of Space Engineering Netherlands University of Rome Department of Electronic Engineering Tor Vergata Italy Information Engineering at the University of Bologna Department of Electrical Electronic Italy

RISC-V-based fault-tolerant system-on-chip (SoC) designs are critical for the new generation of automotive and space SoC architectures. However, reliability assessment requires characterization under controlled radiation doses to accurately quantify the fault tolerance of the fabricated designs. This work analyzes the Trikarenos design, a SoC implemented in TSMC 28nm, for single event upset (SEU) vulnerability under atmospheric neutron and 200MeV proton radiation, comparing these results to simulation-based fault injection. All faults in error correction codes (ECC) protected memory are corrected by a scrubber, showing an estimated cross-section per bit of up to 1.09 × 10−14 cm2 bit−1. Furthermore, the triple-core lockstep (TCLS) mechanism implemented in Trikarenos is validated and is shown to correct errors affecting a cross-section up to 3.23 × 10−11 cm2, with the remaining uncorrectable vulnerability below 5.36 × 10−12 cm2. When augmenting the experimental analysis of fabricated chips with gate-level fault injection in simulation, 99.10% of injections into the SoC produced correct results, while 100% of injections in the TCLS-protected cores were handled *** 12.28%of all injected faults leading to a TCLS recovery, this indicates an approximate effective flip-flop cross-section of up to 1.28 × 10−14 cm2/FF. © 1963-2012 IEEE.

关键词： Radiation damage

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An interactive environment for mapping computational structures to FPGAs 3

An interactive environment for mapping computational structu...

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3rd International Workshop on FPGAs for Software Programmers, FSP 2016, co-located with International Conference on Field Programmable Logic and Applications, FPL 2016

作者： Wester, Rinse De Groote, Robert Computer Architecture for Embedded Systems University of Twente Netherlands

ISBN: (纸本)9783800742660

In this paper we propose a methodology to translate computational structures to hardware. Computational structures express both the computation and the ordering of computations. These structures are expressed using dataflow graphs from which hardware can be generated more directly compared to imperative approaches. As a proof of concept, SDFkit is developed. SDFkit is a cycle accurate simulation and development environment for these computational structures. Additionally, SDFkit has a code generation backend to generate FPGA code. © VDE VERLAG GMBH · Berlin · Offenbach

关键词： Field programmable gate arrays (FPGA)

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