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2019 International Workshop on Petri Nets and Software Engineering, PNSE 2019

作者： Weichenhain, Maxi Fengler, Wolfgang Computer Architecture and Embedded Systems Group Technische Universität Ilmenau Germany

The world of project management (PM) is diverse and extensive, as is the resulting tool selection on the market. Despite the wide variety of tools available, many PM activities are carried out using self-developed spreadsheets that have been tailored to meet the needs of the project. The authors have evaluated experiences from several completed projects and recognizes the need for a systematic model based on a formalised and tool-independent table structure. The goal of this work is to use a powerful Petri net (PN) model for mapping and simulation, taking advantage of the model's benefits. Thus, an effective and flexible methodology for PM can be realised. In order to use the concept of PN for this purpose, appropriated extensions and necessary interpretations from the area of high-level timed Petri nets must be used. Moreover, PM has to be brought to the same description level as PN. The concept of this proposed method is to enter all data, initial plan inputs and intermediate status updates into a defined table structure. A PN is then automatically generated in the background or updated to reflect the current status of the project. Simulations should be performed on the PN models, and their results should be put back into the table. The advantages of the PN concept can thus be fully exploited and become useful for a project manager, even if he or she does not have any PN knowledge. This article presents an overview of the proposed formalised methodology, its suitability to PM, and its benefits. The method itself can be applied to a wide range of projects. Focus is placed on how to transfer certain areas of PM into the introduced PN constructs and interfaces. Examples are used to illustrate how to transform PM activities and their related information into the selected PNs. © 2019 CEUR Workshop Proceedings. All rights reserved.

关键词： Petri nets

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Fault Management Impacts on the Networking systems Hardware Design

Fault Management Impacts on the Networking Systems Hardware ...

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Annual Conference of Industrial Electronics Society

作者： Carlo Vitucci Daniel Sundmark Marcus Jägemar Jakob Danielsson Alf Larsson Thomas Nolte Technology Management Ericsson AB Stockholm Sweden Computer Science and Software Enigineering Mälardalen University Vasterås Sweden Sys Compute Dimensioning Ericsson AB Stockholm Sweden Sys Architecture Ericsson AB Stockholm Sweden Senior Specialist Observability Ericsson AB Stockholm Sweden Networked and Embedded Systems Mälardalen University Västerås Sweden

Processing capacity distribution has become widespread in the fog computing era. End-user services have multiplied, from consumer products to Industry 5.0. In this scenario, the services must have a very high-reliability level. But in a system with such displacement of hardware, the reliability of the service necessarily passes through the hardware design. Devices shall have a high quality, but they shall also efficiently support fault management. Hardware design must take into account all fault management functions and participate in creating a fault management policy to ensure that the ultimate goal of fault management is fulfilled, namely to increase a system's reliability. Efficiently and sustainably, both in the system's performance and the product's cost. This paper analyzes the hardware design techniques that efficiently contribute to the realization of fault management and, consequently, guarantee a high level of reliability and availability for the services offered to the end customer. We describe hardware requirements and how they affect the choice of devices in the hardware design of networking systems.

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Deep Convolutional Autoencoder Applied for Noise Reduction in Range-Doppler Maps of FMCW Radars

Deep Convolutional Autoencoder Applied for Noise Reduction i...

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IEEE International Conference on Radar

作者： Marcio L. Lima de Oliveira Marco J. G. Bekooij Computer Architecture for Embedded Systems University of Twente Enschede The Netherlands NXP Semiconductors Eindhoven The Netherlands

ISBN: (数字)9781728168135

ISBN: (纸本)9781728168142

In this paper, we discuss the usage of deep Convolutional Autoencoders (CAE) for denoising Range-Doppler (RD) maps of an FMCW radar in a near-field situation with pedestrians and cyclists as moving objects. Traditional methods for noise reduction such as CFAR with Peak Detection (PD) have poor performance under highly noisy environments, especially when objects have low reflectivity, like pedestrians. We propose the use of Convolutional Autoencoders, in various configurations, to overcome those limitations. Due to its Artificial Neural Network nature, CAE can extract features, learn to identify patterns and recognize moving objects - such as humans and bicycles - while the traditional method acts passively. The results indicate that the usage of CAE overcame CFAR with PD by 76.8%, on average, for reconstructing objects in their correct positions. The results of this work may have many applications, for instance, detecting distant moving objects that are too faint for regular detection.

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MEPNTC: A Standard-Cell Library Design Scheme Extending the Minimum-Energy-Point Operation of Near-$V_{th}$ Computing

MEPNTC: A Standard-Cell Library Design Scheme Extending the ...

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Anuradha C. Ranasinghe Sabih H. Gerez Chair of Computer Architecture for Embedded Systems Faculty of Electrical Engineering University of Twente Enschede Netherlands

ISBN: (数字)9781728197104

ISBN: (纸本)9781728197111

This paper presents an energy-efficient standard-cell library design scheme: MEPNTC, targeting ultra-low-voltage near/sub- V th operation. MEPNTC exploits an alternative logic style and inverse-narrow-width-effect (INWE) to extend the minimum energy point operation. A carefully engineered design style is presented to improve the PVT and glitch immunity of the cells while preserving balanced noise margins across a wider VDD range. The reduced parasitics and performance boost from both techniques have demonstrated up to 30 % -60 % of energy savings at 0.5V, typical near- V th level for general-purpose hardware accelerator benchmarks (32-bit Booth Multiplier, 25- Tap FIR Filter, Forward Discrete Cosine Transform and JPEG Image Compression Units) compared to standard CMOS and INWE aware CMOS designs in 65-nm bulk CMOS technology.

关键词： Transform coding CMOS technology Libraries Hardware Energy efficiency Standards Resilience

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Generating Synthetic Short-Range FMCW Range-Doppler Maps Using Generative Adversarial Networks and Deep Convolutional Autoencoders

Generating Synthetic Short-Range FMCW Range-Doppler Maps Usi...

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IEEE National Conference on Radar

作者： Marcio L. Lima de Oliveira Marco J. G. Bekooij Computer Architecture for Embedded Systems University of Twente Enschede The Netherlands NXP Semiconductors University of Twente Eindhoven The Netherlands

ISBN: (数字)9781728189420

ISBN: (纸本)9781728189437

In this paper, we discuss the usage of Generative Adversarial Networks (GANs) and Deep Convolutional Autoen-coders (CAE) for creating synthetic Range-Doppler (RD) maps of Frequency-Modulated Continuous-Wave (FMCW) radars for a short-range situation with moving objects, based on measured RD maps of pedestrians and cyclists. Instead of using regular mathematical functions or heavy radar simulations, we have used an Artificial Neural Network (ANN) model to generate new data. By using our synthetic data, we can automatically have ground-truth data without the need for manual labor; easily create large synthetic datasets; hardly use much computational power after training. To evaluate our method, we have trained a detector system with just synthetic data, and it was capable of detecting moving objects correctly, on actual Range-Doppler maps, 11.6% better than when using a small dataset.

关键词： Radar Training Generators Generative adversarial networks Radar imaging Noise measurement Convolution

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Ultra-Low Voltage 4-to-2 Compressors for Near-Vth Computing

Ultra-Low Voltage 4-to-2 Compressors for Near-Vth Computing

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Anuradha C. Ranasinghe Sabih H. Gerez Chair of Computer Architecture for Embedded Systems Faculty of Electrical Engineering University of Twente 5 Drienerlolaan 7522 NB Enschede Netherlands

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

This paper presents two novel circuit arrangements for an ultra-low voltage, low-power 4-to-2 compressor targeting typical near-V th application domain. A hybrid logic style is utilized to exploit energy efficiency by means of parasitic reduction in circuit blocks. Proposed structures are evaluated against prevalent compressors in terms of their typical figure of merits and noise immunity. From extensive post-layout simulations in 65-nm bulk CMOS process technology, the most optimal arrangement was found to be 35% more power efficient, 3.4% faster, 8% more area efficient and 37% better in PDP at 0.4V DD compared to most appealing implementations in literature.

关键词： Transistors Compressors Delays Adders Logic gates Synchronization Inverters

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A Complete Open Source Design Flow for Gowin FPGAs

A Complete Open Source Design Flow for Gowin FPGAs

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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Pepijn de Vos Michael Kirchhoff Daniel Ziener Symbiotic EDA University of Twente Enschede Netherlands Group for Computer Architecture and Embedded Systems Technische Universität Ilmenau Ilmenau Germany

ISBN: (纸本)9781665423021;9781665446228

In this paper, we propose an open source design flow for the low cost FPGAs from the company Gowin. Open source design tools are opening the door for custom extensions and modification in the design flow. The proposed design flow which supports almost all Gowin FPGA resources, is based on well-known open source tools, like Yosys and nextpnr, as well as on our proposed open source bitstream generator. The necessary architectural details of the FPGA family are gathered by input fuzzing and comparisons with the vendor tool flow. Experimental results show an almost similar performance as the vendor tools.

关键词： Companies Tools Logic gates Fuzzing Software Generators Design tools

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Optimizing FPGA-Based Streaming Applications for Throughput Using Pipelining

Optimizing FPGA-Based Streaming Applications for Throughput ...

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IEEE International Conference on Field-Programmable Technology (FPT)

作者： Ali Asghar Rick van Loo Timon Kruiper Daniel Ziener Computer Architecture for Embedded Systems University of Twente

In this paper, we present an automated flow for insertion of pipeline stages in FPGA-based streaming applications in order to increase the throughput. The proposed approach involves the utilization of Xilinx's Automated Pipeline Analysis tool to estimate the number of pipeline stages, while the Rapid-Wright framework incorporate these stages into a synthesized design. The Vivado Design Suite is then used to place and route the modified netlist. Furthermore, a recycling approach has also been proposed to reduce excess registers. The results show a significant improvement in the maximum operating frequency for designs without any sequential loops (~51%) with a moderate resource overhead, while slight gains (~12%) were also observed for designs containing feedback loops.

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Case Study on Design and Evaluation of a Multi-Soft-Core Processor

Case Study on Design and Evaluation of a Multi-Soft-Core Pro...

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International Conference and Workshop on Computing and Communication (IEMCON)

作者： Michael Kirchhoff Lothar Wagner Bernd Däne Detlef Streitferdt Wolfgang Fengler Group for Computer Architecture and Embedded Systems Technische Universität Ilmenau Ilmenau Germany Group for Software Systems and Process Informatics Technische Universität Ilmenau Ilmenau Germany

ISBN: (纸本)9781728125312

Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. The trend for soft-core processors, as well as mainstream CPUs (central processing units), leads to multi-core architectures. Both the necessary memory architectures and the compilers play an important role in this process. In this paper, a novel method that aims at minimizing the necessary memory resources on the FPGA while maximizing the processing speed of any given algorithm is described. In the first step, an application-specializable multi-soft-core processor architecture is presented that is capable of solving problems while adhering to hard real-time deadlines. Its special architecture and other necessary features are discussed. Furthermore, a method for the generation of optimized machine code for each processor core as well as hard real-time compatible deadlock handling mechanisms are presented. Selected algorithms are implemented to demonstrate the functionality and efficiency of the realized approach for different configurations of the multi-soft-core processor architecture.

关键词： Microprocessors Multicore processing Memory architecture Multiprocessor interconnection Field programmable gate arrays Field programmable gate arrays Memory architecture macroprocessor Parallel processor interconnection PROCESSOR soft-core Processor Core embedded system development Processor architectures Mechanical Code central processing units hard real-time

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Self-Awareness for Autonomous systems

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PROCEEDINGS OF THE IEEE 2020年第7期108卷 971-975页

作者： Dutt, Nikil Regazzoni, Carlo S. Rinner, Bernhard Yao, Xin Nikil Dutt (Fellow IEEE) received the Ph.D. degree from the University of Illinois at Urbana–Champaign Champaign IL USA in 1989.""He is currently a Distinguished Professor of computer science (CS) cognitive sciences and electrical engineering and computer sciences (EECS) with the University of California at Irvine Irvine CA USA. He is a coauthor of seven books. His research interests include embedded systems electronic design automation (EDA) computer architecture distributed systems healthcare Internet of Things (IoT) and brain-inspired architectures and computing.""Dr. Dutt is a Fellow of ACM. He was a recipient of the IFIP Silver Core Award. He has received numerous best paper awards. He serves as the Steering Committee Chair of the IEEE/ACM Embedded Systems Week (ESWEEK). He is also on the steering organizing and program committees of several premier EDA and embedded system design conferences and workshops. He has served on the Editorial Boards for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems and the ACM Transactions on Embedded Computing Systems and also previously served as the Editor-in-Chief (EiC) for the ACM Transactions on Design Automation of Electronic Systems. He served on the Advisory Boards of the IEEE Embedded Systems Letters the ACM Special Interest Group on Embedded Systems the ACM Special Interest Group on Design Automationt and the ACM Transactions on Embedded Computing Systems. Carlo S. Regazzoni (Senior Member IEEE) received the M.S. and Ph.D. degrees in electronic and telecommunications engineering from the University of Genoa Genoa Italy in 1987 and 1992 respectively.""He is currently a Full Professor of cognitive telecommunications systems with the Department of Electrical Electronics and Telecommunication Engineering and Naval Architecture (DITEN) University of Genoa and a Co-Ordinator of the Joint Doctorate on Interactive and Cognitive Environments (JDICE) international Ph.D. course started initially as EU Erasmus Mundus Project and

Autonomous systems are able to make decisions and potentially take actions without direct human intervention, which requires some knowledge about the system and its environment as well as goal-oriented reasoning. In computer systems, one can derive such behavior from the concept of a rational agent with autonomy (“control over its own actions”), reactivity (“react to events from the environment”), proactivity (“act on its own initiative”), and sociality (“interact with other agents”) as fundamental properties \n[1]\n. Autonomous systems will undoubtedly pervade into our everyday lives, and we will find them in a variety of domains and applications including robotics, transportation, health care, communications, and entertainment to name a few. \nThe articles in this month’s special issue cover concepts and fundamentals, architectures and techniques, and applications and case studies in the exciting area of self-awareness in autonomous systems.

关键词： Special issues and sections Autonomous systems Self-aware Robot sensing systems Computational modeling

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