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arXiv 2018年

作者： Posewsky, Thorbjörn Ziener, Daniel Hamburg21073 Germany Computer Architecture for Embedded Systems University of Twente Enschede7500 AE Netherlands

Deep neural networks are an extremely successful and widely used technique for various pattern recognition and machine learning tasks. Due to power and resource constraints, these computationally intensive networks are difficult to implement in embedded systems. Yet, the number of applications that can benefit from the mentioned possibilities is rapidly rising. In this paper, we propose novel architectures for the inference of previously learned and arbitrary deep neural networks on FPGAbased SoCs that are able to overcome these limitations. Our key contributions include the reuse of previously transferred weight matrices across multiple input samples, which we refer to as batch processing, and the usage of compressed weight matrices, also known as pruning. An extensive evaluation of these optimizations is presented. Both techniques allow a significant mitigation of data transfers and speed-up the network inference by one order of magnitude. At the same time, we surpass the data throughput of fully-featured x86-based systems while only using a fraction of their energy consumption. Copyright © 2018, The Authors. All rights reserved.

关键词： Deep neural networks

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DEFINITION OF A TRANSPARENT CONSTRAINT-BASED MODELING AND SIMULATION LAYER FOR THE MANAGEMENT OF COMPLEX systems

DEFINITION OF A TRANSPARENT CONSTRAINT-BASED MODELING AND SI...

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Simulation Multi-Conference

作者： Kevin Henares Jose L. Risco-Martin Marina Zapater Dept. of Computer Architecture and Automation Complutense University of Madrid Madrid Spain Embedded Systems Laboratory (ESL) Swiss Federal Institute of Technology Lausanne (EPFL) Lausanne Switzerland

Modeling and Simulation (M&S) is one of the most multifaceted topics present today in both industry and academia. However, we are involved in a new M&S paradigm. systems are becoming more complex and new simulation needs arise and have to be studied. As a consequence, the way in which we perform M&S must be adapted, providing new ideas and tools. In this paper, we propose a rule-based constraints evaluator, which facilitate the validation and verification of complex models in a transparent manner. For this, constraints are defined. The constraints definition process is completely independent of the model development process because (a) the set of constraints is defined once the model has been developed, and (b) constraints are validated at simulation time. The proposed Constraint M&S architecture has been built using the Discrete Event System Specification (DEVS) formalism and has been tested on a validated data center simulation model.

关键词： Model checking Constraint modeling and simulation Discrete events Verification Data centers

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An interactive environment for mapping computational structures to FPGAs

An interactive environment for mapping computational structu...

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FSP 2016;Third International Workshop on FPGAs for Software Programmers

作者： Rinse Wester Robert de Groote Computer Architecture for Embedded Systems University of Twente

In this paper we propose a methodology to translate computational structures to hardware. Computational structures express both the computation and the ordering of computations. These structures are expressed using dataflow graphs from which hardware can be generated more directly compared to imperative approaches. As a proof of concept, SDFkit is developed. SDFkit is a cycle accurate simulation and development environment for these computational structures. Additionally, SDFkit has a code generation backend to generate FPGA code.

关键词： Code generation Field programmable gate arrays Interactive environment computer hardware data flow MAPPING(MATHEMATICAL) mapping

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eQASM: An executable quantum instruction set architecture

arXiv

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arXiv 2018年

作者： Fu, X. Riesebos, L. Rol, M.A. van Straten, J. van Someren, J. Khammassi, N. Ashraf, I. Vermeulen, R.F.L. Newsum, V. Loh, K.K.L. de Sterke, J.C. Vlothuizen, W.J. Schouten, R.N. Almudever, C.G. DiCarlo, L. Bertels, K. QuTech Delft University of Technology P.O. Box 5046 Delft2600 GA Netherlands Quantum Computer Architecture Lab Delft University of Technology Mekelweg 4 Delft2628 CD Netherlands Kavli Institute of Nanoscience Delft University of Technology P.O. Box 5046 Delft2600 GA Netherlands Computer Engineering Lab Delft University of Technology Mekelweg 4 Delft2628 CD Netherlands P.O. Box 155 Delft2600 AD Netherlands Topic Embedded Systems B.V. P.O. Box 440 AK Best5680 Netherlands

A widely-used quantum programming paradigm comprises of both the data flow and control flow. Existing quantum hardware cannot well support the control flow, significantly limiting the range of quantum software executable on the hardware. By analyzing the constraints in the control microarchitecture, we found that existing quantum assembly languages are either too high-level or too restricted to support comprehensive flow control on the hardware. Also, as observed with the quantum microinstruction set QuMIS [1], the quantum instruction set architecture (QISA) design may suffer from limited scalability and flexibility because of microarchitectural constraints. It is an open challenge to design a scalable and flexible QISA which provides a comprehensive abstraction of the quantum hardware. In this paper, we propose an executable QISA, called eQASM, that can be translated from quantum assembly language (QASM), supports comprehensive quantum program flow control, and is executed on a quantum control microarchitecture. With efficient timing specification, single-operation-multiple-qubit execution, and a very-long-instruction-word architecture, eQASM presents better scalability than QuMIS. The definition of eQASM focuses on the assembly level to be expressive. Quantum operations are configured at compile time instead of being defined at QISA design time. We instantiate eQASM into a 32-bit instruction set targeting a seven-qubit superconducting quantum processor. We validate our design by performing several experiments on a two-qubit quantum processor. Copyright © 2018, The Authors. All rights reserved.

关键词： computer architecture

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Accurate dead code detection in embedded C code by arithmetic constraint solving 1

Accurate dead code detection in embedded C code by arithmeti...

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1st Workshop on Satisfiability Checking and Symbolic Computation, SC-Square 2016

作者： Neubauer, Felix Scheibler, Karsten Becker, Bernd Mahdi, Ahmed Fränzle, Martin Teige, Tino Bienmüller, Tom Fehrer, Detlef Department of Computer Architecture University of Freiburg Germany Research Group Hybrid Systems Carl von Ossietzky University of Oldenburg Germany BTC Embedded Systems AG Oldenburg Germany Sick AG Waldkirch Germany

Unreachable code fragments in software, despite not having a negative impact on the functional behavior, can have a bad effect in other areas, such as code optimization or coverage-based code validation and certification. Especially the latter is important in industrial, safety critical environments, where detecting such dead code is a major goal to adjust the coverage of software tests. In the context of embedded systems we focus on C programs which are reactive, control-oriented, and floating-point dominated. Such programs are either automatically generated from Simulink-plus-Stateflow models or hand-written according to coding guidelines. While there are various techniques - e. g. abstract interpretation or Counterexample guided abstraction refinement (CEGAR) - to deal with individual issues of this domain, there is none which can cover all of them. The AVACS transfer project T1 aims at the combination of these techniques in order to provide an accurate and efficient dead code detection. In this paper we present the ideas and goals of the project as well as the current status (including very promising experimental results) and future challenges. Copyright © by the paper's authors.

关键词： Formal verification

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Accurate ICP-based floating-point reasoning 16

Accurate ICP-based floating-point reasoning

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Formal Methods in computer Aided Design (FMCAD)

作者： Karsten Scheibler Felix Neubauer Ahmed Mahdi Martin Fränzle Tino Teige Tom Bienmüller Detlef Fehrer Bernd Becker Chair of Computer Architecture University of Freiburg Germany Research Group Hybrid Systems Carl von Ossietzky University of Oldenburg Germany BTC Embedded Systems AG Oldenburg Germany Sick AG Waldkirch Germany

ISBN: (纸本)9780983567868

In scientific and technical software, floating-point arithmetic is often used to approximate arithmetic on physical quantities natively modeled as reals. Checking properties for such programs (e.g. proving unreachability of code fragments) requires accurate reasoning over floating-point arithmetic. Currently, most of the SMT-solvers addressing this problem class rely on bit-blasting. Recently, methods based on reasoning in interval lattices have been lifted from the reals (where they traditionally have been successful) to the floating-point numbers. The approach presented in this paper follows the latter line of interval-based reasoning, but extends it by including bitwise integer operations and cast operations between integer and floating-point arithmetic. Such operations have hitherto been omitted, as they tend to define sets not concisely representable in interval lattices, and were consequently considered the domain of bit-blasting approaches. By adding them to interval-based reasoning, the full range of basic data types and operations of C programs is supported. Furthermore, we propose techniques in order to mitigate the problem of aliasing during interval reasoning. The experimental results confirm the efficacy of the proposed techniques. Our approach outperforms solvers relying on bit-blasting as well as the existing interval-based SMT-solver.

关键词： Cognition Lattices Iterative closest point algorithm Open area test sites Context Computational modeling Encoding

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Multi-layer test and diagnosis for dependable NoCs 15

Multi-layer test and diagnosis for dependable NoCs

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9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015

作者： Wunderlich, Hans-Joachim Radetzki, Martin Computer Architecture University of Stuttgart Pfaffenwaldring 47 StuttgartD-70569 Germany Embedded Systems Engineering University of Stuttgart Pfaffenwaldring 5b StuttgartD-70569 Germany

ISBN: (纸本)9781450333962

Networks-on-chip are inherently fault tolerant or at least gracefully degradable as both, connectivity and amount of resources, provide some useful redundancy. These properties can only be exploited extensively if test and diagnosis techniques support fault detection and error containment in an optimized way. On the one hand, all faulty components have to be isolated, and on the other hand, remaining fault-free functionalities have to be kept operational. In this contribution, behavioral end-to-end error detection is considered together with functional test methods for switches and gate level diagnosis to locate and to isolate faults in the network in an efficient way with low time overhead. © 2015 ACM.

关键词： Network-on-chip

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STRAP: Stress-aware placement for aging mitigation in runtime reconfigurable architectures 15

STRAP: Stress-aware placement for aging mitigation in runtim...

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IEEE International Conference on computer-Aided Design

作者： Hongyan Zhang Michael A. Kochte Eric Schneider Lars Bauer Hans-Joachim Wunderlich Jörg Henkel Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany Institute of Computer Architecture and Computer Engineering University of Stuttgart Germany

ISBN: (纸本)9781467383899

Aging effects in nano-scale CMOS circuits impair the reliability and Mean Time to Failure (MTTF) of embedded systems. Especially for FPGAs that are manufactured in the latest technology node, aging is amajor concern. We introduce the first cross-layer aging-aware placement method for accelerators in FPGA-based runtime reconfigurable architectures. It optimizes stress distribution by accelerator placement at runtime, i.e. to which reconfigurable region an accelerator shall be reconfigured. Additionally, it optimizes logic placement at synthesis time to diversify the resource usage of individual accelerators, i.e. which CLBs of a reconfigurable region shall be used by an accelerator. Both layers together balance the intra- and inter-region stress induced by the application workload at negligible performance cost. Experimental results show significant reduction of maximum stress of up to 64% and 35%, which leads to up to 177% and 14% MTTF improvement relative to state-of-the-art methods w.r.t. HCI and BTI aging, respectively.

关键词： Stress Runtime Aging Transistors Table lookup Fabrics Field programmable gate arrays

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A dataflow inspired programming paradigm for coarse-grained reconfigurable arrays

A dataflow inspired programming paradigm for coarse-grained ...

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10th International Symposium on Reconfigurable Computing: architectures, Tools, and Applications, ARC 2014

作者： Niedermeier, A. Kuper, Jan Smit, Gerard J. M. Computer Architecture for Embedded Systems Group Department of Electrical Engineering Mathematics and Computer Science University of Twente Netherlands

ISBN: (纸本)9783319059594

In this paper, we present a new approach towards programming coarse-grained reconfigurable arrays (CGRAs) in an intuitive, dataflow inspired way. Based on the observation that available CGRAs are usually programmed using C, which lacks proper support for instruction-level parallelism, we instead started from a dataflow perspective combined with a language that inherently supports parallel structures. Our programming paradigm decouples the local functionality of a core from the global flow of data, i.e. the kernels from the routing. We will describe the ideas of our programming paradigm and also the language and compiler itself. Our complete system, including the CGRA, the programming language and the compiler, was developed using Haskell, which leads to a complete, sound system. We finish the paper with the implementation of a number of algorithms using our system. © 2014 Springer International Publishing Switzerland.

关键词： Program compilers

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Temperature-aware software-based self-testing for delay faults 15

Temperature-aware software-based self-testing for delay faul...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Ying Zhang Zebo Peng Jianhui Jiang Huawei Li Masamro Fujita School of Software Engineering Tongji University China Embedded Systems Lab Linköping University Sweden State Key Laboratory of Computer Architecture Chinese Academy of Sciences China VLSI Design and Education Center University of Tokyo Japan

ISBN: (纸本)9783981537048

Delay defects under high temperature have been one of the most critical factors to affect the reliability of computer systems, and the current test methods don't address this problem properly. In this paper, a temperature-aware software-based self-testing (SBST) technique is proposed to self-heat the processors within a high temperature range and effectively test delay faults under high temperature. First, it automatically generates high-quality test programs through automatic test instruction generation (ATIG), and avoids over-testing caused by nonfunctional patterns. Second, it exploits two effective powerintensive program transformations to self-heat up the processors internally. Third, it applies a greedy algorithm to search the optimized schedule of the test templates in order to generate the test program while making sure that the temperature of the processor under test is within the specified range. Experimental results show that the generated program is successful to guarantee delay test within the given temperature range, and achieves high test performance with functional patterns.

关键词： Delays Program processors Temperature distribution Power dissipation Circuit faults Schedules

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