检索结果-内蒙古大学图书馆

作者： Geuns, Stefan J. Hausmans, Joost P. H. M. Bekooij, Marco J. G. Computer Architecture for Embedded Systems University of Twente Netherlands NXP Semiconductors Netherlands and Computer Architecture for Embedded Systems University of Twente Netherlands

Automatic parallelization of Nested Loop Programs (NLPs) is an attractive method to create embedded realtime stream processing applications for multi-core systems. However, the description and parallelization of applications with a time dependent functional behavior has not been considered in NLPs. In such a description, semantic information about time dependent behavior must be made available for the compiler, such that an optimized time independent implementation can be generated automatically. This article introduces language constructs with temporal semantics to NLPs. Using these language constructs, time dependent applications can be specified and a corresponding data-driven implementation can be generated for use on a multi-core system. Despite that these time-aware language constructs can be data-dependent, the application remains functionally deterministic. Pipelining is exploited to increase the throughput of an application. The media access control (MAC) protocol of an IEEE 802.11p WLAN transceiver is used to illustrate the relevance and applicability of the introduced concepts. © 2013 ACM.

关键词： Application programs

来源：评论

学校读者我要写书评

暂无评论

Designing a control application by using a specialized multi-core soft microprocessor

Designing a control application by using a specialized multi...

引用

12th IFAC Conference on Programmable Devices and embedded systems, PDeS 2013

作者： Däne, Bernd Pacholik, Alexander Zschäck, Stephan Fengler, Wolfgang Ament, Christoph Braune, Tobias Computer Architecture and Embedded Systems Group Ilmenau University of Technology 98684 Ilmenau Germany Systems Analysis Group Ilmenau University of Technology 98684 Ilmenau Germany

ISBN: (纸本)9783902823533

Computationally intensive algorithms for closed loop control and similar systems today can be implemented using reconfigurable FPGA devices. One approach is using soft microprocessor designs and implementing the algorithms as programs. This paper reports about a case study within an ongoing project that investigates a multi-core soft microprocessor solution for a closed-loop control application. Requirements within the project lead to a specialized processor design. Some results from experimental work are presented, demonstrating feasibility and efficiency of the approach. © IFAC.

关键词： Signal processing

来源：评论

学校读者我要写书评

暂无评论

A dataflow-inspired CGRA for streaming applications

A dataflow-inspired CGRA for streaming applications

引用

International Conference on Field Programmable Logic and Applications

作者： Anja Niedermeier Jan Kuper Gerard J.M. Smit Faculty of Electrical Engineering Mathematics and Computer Science Computer Architecture Embedded Systems University of Twente Netherlands

The herein presented research is motivated by the need for reconfigurable, flexible computing arrays targeted at streaming applications that contain a large degree of instruction-level parallelism. Such arrays are usually referred to as coarse-grained reconfigurable arrays (CGRAs). CGRAs are composed of small, reconfigurable cores that are interconnected to form a computing grid. Here, we present a complete CGRA, consisting of an architecture and a programming language. Both the architecture and the programming language are inspired by the principles found in dataflow.

关键词： computer architecture Programming Registers Program processors Parallel processing computer languages Vectors

来源：评论

学校读者我要写书评

暂无评论

Designing a Control Application by Using a Specialized Multi-Core Soft Microprocessor

引用

IFAC Proceedings Volumes 2013年第28期46卷 221-226页

作者： Bernd Däne Alexander Pacholik Stephan Zschäck Wolfgang Fengler Christoph Ament Tobias Braune Computer Architecture and Embedded Systems Group Systems Analysis Group Ilmenau University of Technology 98684 Ilmenau Germany Tel: +49-3677-69-2825)

关键词： embedded systems soft microprocessor signal processing floating-point real-time

来源：评论

学校读者我要写书评

暂无评论

Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures

Module diversification: Fault tolerance and aging mitigation...

引用

IEEE International Test Conference

作者： Hongyan Zhang Lars Bauer Michael A. Kochte Eric Schneider Claus Braun Michael E. Imhof Hans-Joachim Wunderlich Jörg Henkel Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany Institute of Computer Architecture and Computer Engineering University of Stuttgart Germany

ISBN: (纸本)9781479908608

Runtime reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are attractive for realizing complex applications. However, being manufactured in latest semiconductor process technologies, FPGAs are increasingly prone to aging effects, which reduce the reliability of such systems and must be tackled by aging mitigation and application of fault tolerance techniques. This paper presents module diversification, a novel design method that creates different configurations for runtime reconfigurable modules. Our method provides fault tolerance by creating the minimal number of configurations such that for any faulty Configurable Logic Block (CLB) there is at least one configuration that does not use that CLB. Additionally, we determine the fraction of time that each configuration should be used to balance the stress and to mitigate the aging process in FPGA-based runtime reconfigurable systems. The generated configurations significantly improve reliability by fault-tolerance and aging mitigation.

关键词： Stress Circuit faults Aging Runtime Field programmable gate arrays Containers Reliability

来源：评论

学校读者我要写书评

暂无评论

Certifiable Development Process for Information Processing in the Measurement Domain on the Base of 3W-Models

Certifiable Development Process for Information Processing i...

引用

IEEE Annual computer Software and Applications Conference Workshops (COMPSACW)

作者： Irina Gushchina Wolfgang Fengler Jirka Ciemala Detlef Streitferdt Computer Architecture and Embedded Systems Group Ilmenau University of Technology Ilmenau Germany Software Architectures and Product Lines Group Ilmenau University of Technology Ilmenau Germany

The paper presents a certifiable development process applicable to hardware and software development for information processing in the measurement domain, especially the dynamic weighing technology. Thereby it is based on the developments of prototypes for new and predecessor systems and product stages. Particular attention is paid to the possibility of calibration.

关键词： Prototypes Mathematical model embedded systems Hardware Safety Measurement uncertainty Field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

High level structural description of streaming applications

High level structural description of streaming applications

引用

22nd International Conference on Field Programmable Logic and Applications, FPL 2012

作者： Niedermeier, Anja Kuper, Jan Smit, Gerard J.M. Faculty of Electrical Engineering Mathematics and Computer Science Computer Architecture Embedded Systems University of Twente Netherlands

ISBN: (纸本)9781467322560

Motivated by the need to describe the structure of streaming applications on a high level of abstraction, we designed a compiler prototype based on the functional programming language Haskell, which by itself already has a notion of structure. We showed how the proposed language was implemented and also how it can be used to describe the structure of a streaming application and how this description can be used to map the application to a hardware architecture. © 2012 IEEE.

关键词： High level languages

来源：评论

学校读者我要写书评

暂无评论

Improving harmonic rejection for spectrum sensing using crosscorrelation

Improving harmonic rejection for spectrum sensing using cros...

引用

38th European Solid State Circuits Conference, ESSCIRC 2012

作者： Oude Alink, Mark S. Kokkeler, André B. J. Klumperink, Eric A. M. Ru, Zhiyu Cheng, Wei Nauta, Bram Integrated Circuit Design/Computer Architecture for Embedded Systems CTIT Research Institute University of Twente Enschede Netherlands

ISBN: (纸本)9781467322126

Harmonic downmixing may cause a spectrum sensing device to erroneously flag parts of the spectrum as occupied. Receivers employing harmonic rejection (HR) rarely obtain more than 60 dB of HR, which may not be enough for spectrum sensing for dynamic spectrum access. We improve HR by employing two RF-receivers, integrated in a single 65nm CMOS IC, and using a small offset in their LO-frequencies. The offset is corrected in the digital baseband, after which the final receiver outputs are crosscorrelated. Our measurements show that the HR can be significantly improved without calibration or time penalty, even for high initial HR, but that the improvement is limited by crosstalk between the receivers. © 2012 IEEE.

关键词： Spectrum analyzers

来源：评论

学校读者我要写书评

暂无评论

A CMOS spectrum analyzer frontend for cognitive radio achieving +25dBm IIP3 and -169 dBm/Hz DANL

A CMOS spectrum analyzer frontend for cognitive radio achiev...

引用

2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012

作者： Oude Alink, Mark S. Klumperink, Eric A.M. Kokkeler, André B.J. Cheng, Wei Ru, Zhiyu Ghaffari, Amir Wienk, Gerard J.M. Nauta, Bram Integrated Circuit Design/Computer Architecture for Embedded Systems CTIT Research Institute University of Twente Enschede Netherlands

ISBN: (纸本)9781467304146

A dual RF-receiver preceded by discrete-step attenuators is implemented in 65nm CMOS and operates from 0.3-1.0 GHz. The noise of the receivers is reduced by cross-correlating the two receiver outputs in the digital baseband, allowing attenuation of the RF input signal to increase linearity. With this technique a displayed average noise level below -169 dBm/Hz is obtained with +25 dBm IIP3, giving a spurious-free dynamic range of 89 dB in 1 MHz resolution bandwidth. © 2012 IEEE.

关键词： Noise figure

来源：评论

学校读者我要写书评

暂无评论

A predictor-based power-saving policy for DRAM memories

A predictor-based power-saving policy for DRAM memories

引用

15th Euromicro Conference on Digital System Design, DSD 2012

作者： Thomas, Gervin Chandrasekar, Karthik Åkesson, Benny Juurlink, Ben Goossens, Kees Technische Universität Berlin Department of Computer Engineering and Microelectronics Embedded Systems Architecture Berlin Germany Technische Universiteit Delft Department of Computer Engineering Delft Netherlands Technische Universiteit Eindhoven Department of Electrical Engineering Electronic Systems Eindhoven Netherlands

ISBN: (纸本)9780769547985

Reducing power/energy consumption is an important goal for all computer systems, from servers to battery-driven hand-held devices. To achieve this goal, the energy consumption of all system components needs to be reduced. One of the most power-hungry components is the off-chip DRAM, even when it is idle. DRAMs support different power-saving modes, such as self-refresh and power-down, but employing them every time the DRAM is idle, reduces performance due to their power-up latencies. The self-refresh mode offers large power savings, but incurs a long power-up latency. The power-down mode, on the other hand, has a shorter power-up latency, but provides lower power savings. In this paper, we propose and evaluate a novel power-saving policy that combines the best of both power-saving modes in order to achieve significant power reductions with a marginal performance penalty. To accomplish this, we use a history-based predictor to forecast the duration of an idle period and then either employ self-refresh, or power-down, or a combination of both power saving modes. Significant refinements are made to the predictor to maximize the energy savings and minimize the performance penalty. The presented policy is evaluated using several applications from the multimedia domain and the experimental results show that it reduces the total DRAM energy consumption between 68.8% and 79.9% at a negligible performance penalty between 0.3% and 2.2%. © 2012 IEEE.

关键词： Dynamic random access storage

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：