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检索条件"机构=The Computer Architecture for Embedded Systems"

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High level structural description of streaming applications

High level structural description of streaming applications

引用

International Conference on Field Programmable Logic and Applications

作者： Anja Niedermeier Jan Kuper Gerard J.M. Smit Faculty of Electrical Engineering Mathematics and Computer Science Computer Architecture Embedded Systems University of Twente Netherlands

The research has been motivated by the desire for a straightforward implementation of an application described as a dataflow graph on a multicore architecture. The design has been based on an already existing language that inherently has a notion of structure: the functional programming language Haskell. Haskell has been used both for embedding the grammar for proposed language as well as to describe streaming applications with the proposed language.

关键词： Production Kernel computer architecture Functional programming Grammar Syntactics Hardware

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Transparent structural online test for reconfigurable systems

Transparent structural online test for reconfigurable system...

引用

IEEE Symposium on On-Line Testing (IOLTS)

作者： Mohamed S. Abdelfattah Lars Bauer Claus Braun Michael E. Imhof Michael A. Kochte Hongyan Zhang Jörg Henkel Hans-Joachim Wunderlich Institute of Computer Architecture and Computer Engineering University of Stuttgart Germany Chair for Embedded Systems Karlsruhe Institute of Technology Germany

FPGA-based reconfigurable systems allow the online adaptation to dynamically changing runtime requirements. However, the reliability of modern FPGAs is threatened by latent defects and aging effects. Hence, it is mandatory to ensure the reliable operation of the FPGA's reconfigurable fabric. This can be achieved by periodic or on-demand online testing. In this paper, a system-integrated, transparent structural online test method for runtime reconfigurable systems is proposed. The required tests are scheduled like functional workloads, and thorough optimizations of the test overhead reduce the performance impact. The proposed scheme has been implemented on a reconfigurable system. The results demonstrate that thorough testing of the reconfigurable fabric can be achieved at negligible performance impact on the application.

关键词： Containers Field programmable gate arrays Testing Table lookup Runtime Random access memory Fabrics

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Investigating dependability of short-range wireless embedded systems through hardware platform based design

Investigating dependability of short-range wireless embedded...

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15th Euromicro Conference on Digital System Design, DSD 2012

作者： Senouci, B. Annema, A.J. Bentum, M.J. Kerkhoff, H.G. Integrated Circuit Design Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Telecommunication Engineering Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Computer Architecture for Embedded Systems /TDT Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands

ISBN: (纸本)9780769547985

Most of the links in future wireless communication networks will be established over relatively short distances. This new direction in wireless communication is adopted and being developed by embedded multimedia applications leaders. Moreover, these short range communications are introduced into critical applications, where the dependability/reliability is mandatory. Thus, dependability concerns around reliability evaluation becomes an essential question to answer, and poses several challenges. Obviously, it's particularly difficult to investigate the reliability of such mixed HW/SW IPs based systems. Therefore, dependability has to be investigated at different abstractions levels, and for all components integrated into the system being designed. In this paper, we discuss the investigation of dependability in wireless short range systems. Firstly we show how a HW platform based dependability investigation can be a very interactive approach;secondly, we describe a real experience in building a wireless hardware platform for short range systems dependability analysis, and finally, based on this wireless network platform, we propose a dependability flow that takes care of the heterogeneous parts of the wireless embedded systems. © 2012 IEEE.

关键词： Reliability

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Improving harmonic rejection for spectrum sensing using crosscorrelation

Improving harmonic rejection for spectrum sensing using cros...

引用

European Conference on Solid-State Circuits (ESSCIRC)

作者： M.S. Oude Alink André B.J. Kokkeler Eric A. M. Klumperink Zhiyu Ru Wei Cheng Bram Nauta Integrated Circuit Design/Computer Architecture for Embedded Systems CTIT Research Institute University of Twente Enschede The Netherlands

Harmonic downmixing may cause a spectrum sensing device to erroneously flag parts of the spectrum as occupied. Receivers employing harmonic rejection (HR) rarely obtain more than 60 dB of HR, which may not be enough for spectrum sensing for dynamic spectrum access. We improve HR by employing two RF-receivers, integrated in a single 65nm CMOS IC, and using a small offset in their LO-frequencies. The offset is corrected in the digital baseband, after which the final receiver outputs are crosscorrelated. Our measurements show that the HR can be significantly improved without calibration or time penalty, even for high initial HR, but that the improvement is limited by crosstalk between the receivers.

关键词： Receivers Harmonic analysis Mixers Sensors Crosstalk Frequency measurement Radio frequency

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A CMOS spectrum analyzer frontend for cognitive radio achieving +25dBm IIP3 and −169 dBm/Hz DANL

A CMOS spectrum analyzer frontend for cognitive radio achiev...

引用

IEEE Symposium on Radio Frequency Integrated Circuits (RFIC)

作者： Mark S. Oude Alink Eric A.M. Klumperink André B.J. Kokkeler Wei Cheng Zhiyu Ru Amir Ghaffari Gerard J.M. Wienk Bram Nauta Integrated Circuit Design / Computer Architecture for Embedded Systems CTIT Research Institute University of Twente Enschede Netherlands

A dual RF-receiver preceded by discrete-step attenuators is implemented in 65nm CMOS and operates from 0.3-1.0 GHz. The noise of the receivers is reduced by cross-correlating the two receiver outputs in the digital baseband, allowing attenuation of the RF input signal to increase linearity. With this technique a displayed average noise level below -169 dBm/Hz is obtained with +25 dBm IIP 3 , giving a spurious-free dynamic range of 89 dB in 1 MHz resolution bandwidth.

关键词： Receivers Noise Noise measurement Attenuation Linearity CMOS integrated circuits Attenuators

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A multi-lead ECG classification based on random projection features

A multi-lead ECG classification based on random projection f...

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International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Iva Bogdanova Francisco Rincón David Atienza Embedded Systems Laboratory (ESL) Ecole Polytechnique Fédérale de Lausanne Switzerland Department of Computer Architecture and Automation Complutense University of Madrid Spain

This paper presents a novel method for classification of multi-lead electrocardiogram (ECG) signals. The feature extraction is based on the random projection (RP) concept for dimensionality reduction. Furthermore, the classification is performed by a neuro-fuzzy classifier. Such a model can be easily implemented on portable systems for practical applications in both health monitoring and diagnostic purposes. Moreover, the RP implementation on portable systems is very challenging featuring both energy efficiency and feasibility. The proposed method is tested on a 12-lead ECG database consisting of 20 beats during normal sinus rhythm, 20 beats with myocardial infarction and 20 beats showing cardiomyopathy for 60 different subjects. The experiments give a recognition rate of 100% for a small number of RP coefficients (only 25), i.e. after a considerable dimensionality reduction of the input ECG signal. The results are very promising, not only from the classification performance point of view, but also while targeting a low-complexity feature extraction in terms of computation requirements and memory usage for real-time operation on a wireless wearable sensor platform.

关键词： Electrocardiography Feature extraction Databases Pragmatics Wireless sensor networks Wireless communication computer architecture

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A Predictor-Based Power-Saving Policy for DRAM Memories

A Predictor-Based Power-Saving Policy for DRAM Memories

引用

Euromicro Symposium on Digital System Design

作者： Gervin Thomas Karthik Chandrasekar Benny Åkesson Ben Juurlink Kees Goossens Department of Computer Engineering and Microelectronics Embedded Systems Architecture Technische Universität Berlin Berlin Germany Department of Computer Engineering Technische Universiteit Delft Delft Netherlands Department of Electrical Engineering Electronic Systems Technische Universiteit Eindhoven Eindhoven Netherlands

Reducing power/energy consumption is an important goal for all computer systems, from servers to battery-driven hand-held devices. To achieve this goal, the energy consumption of all system components needs to be reduced. One of the most power-hungry components is the off-chip DRAM, even when it is idle. DRAMs support different power-saving modes, such as self-refresh and power-down, but employing them every time the DRAM is idle, reduces performance due to their power-up latencies. The self-refresh mode offers large power savings, but incurs a long power-up latency. The power-down mode, on the other hand, has a shorter power-up latency, but provides lower power savings. In this paper, we propose and evaluate a novel power-saving policy that combines the best of both power-saving modes in order to achieve significant power reductions with a marginal performance penalty. To accomplish this, we use a history-based predictor to forecast the duration of an idle period and then either employ self-refresh, or power-down, or a combination of both power saving modes. Significant refinements are made to the predictor to maximize the energy savings and minimize the performance penalty. The presented policy is evaluated using several applications from the multimedia domain and the experimental results show that it reduces the total DRAM energy consumption between 68.8% and 79.9% at a negligible performance penalty between 0.3% and 2.2%.

关键词： Random access memory History Clocks Energy consumption Prediction algorithms Memory management Servers

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Investigating Dependability of Short-Range Wireless embedded systems through Hardware Platform Based Design

Investigating Dependability of Short-Range Wireless Embedded...

引用

Euromicro Symposium on Digital System Design

作者： B. Senouci A.J. Annema M.J. Bentum H.G. Kerkhoff Integrated Circuit Design Group Electrical Engineering Mathematics and Computer Science Faculty Telecommunication Engineering Group Computer Architecture for Embedded Systems /TDT Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Integrated Circuit Design Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands Telecommunication Engineering Group University of Twente Enschede Netherlands Computer Architecture for Embedded Systems /TDT Group Electrical Engineering Mathematics and Computer Science Faculty University of Twente Enschede Netherlands

Most of the links in future wireless communication networks will be established over relatively short distances. This new direction in wireless communication is adopted and being developed by embedded multimedia applications leaders. Moreover, these short range communications are introduced into critical applications, where the dependability/reliability is mandatory. Thus, dependability concerns around reliability evaluation becomes an essential question to answer, and poses several challenges. Obviously, it's particularly difficult to investigate the reliability of such mixed HW/SW IPs based systems. Therefore, dependability has to be investigated at different abstractions levels, and for all components integrated into the system being designed. In this paper, we discuss the investigation of dependability in wireless short range systems. Firstly we show how a HW platform based dependability investigation can be a very interactive approach; secondly, we describe a real experience in building a wireless hardware platform for short range systems dependability analysis, and finally, based on this wireless network platform, we propose a dependability flow that takes care of the heterogeneous parts of the wireless embedded systems.

关键词： Wireless communication Hardware Software computer architecture Communication system security Reliability System-on-a-chip

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LiSARD: LabVIEW integrated softcore architecture for reconfigurable devices

LiSARD: LabVIEW integrated softcore architecture for reconfi...

引用

2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011

作者： Pacholik, A. Klockner, J. Muller, M. Gushchina, I. Fengler, W. Computer Architecture and Embedded Systems Group Ilmenau University of Technology 98684 Ilmenau Germany

ISBN: (纸本)9780769545516

The development of industrial control and measurement systems is often based on modular commercial off the-shelf hardware. Lately, for these platforms reconfigurable I/O modules with field-programmable gate arrays (FPGA) have gained significance, since they allow the implementation of data processing functionality very close to the data acquisition interfaces. However, algorithm complexity and floating-point support are limited by FGPA resources and design methods. This contribution presents an application specific configurable DSP soft core architecture built around a scalable double precision floating-point arithmetic/logic unit. The core can be seamlessly utilized as a functional component in Lab VIEW based FPGA designs. A small case study shows the performance of an example application implemented on the presented core in comparison to other embedded architectures. © 2011 IEEE.

关键词： Digital arithmetic

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Multicore soc for on-board payload signal processing

Multicore soc for on-board payload signal processing

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NASA/ESA Conference on Adaptive Hardware and systems

作者： Walters, Karel H.G. Gerez, S.H. Smit, G.J.M. Baillou, S. Rauwerda, G.K. Trautner, R. Computer Architecture for Embedded Systems University of Twente Enschede Netherlands Recore Systems Enschede Netherlands European Space Agency ESTEC Noordwijk Netherlands

ISBN: (纸本)9781457705984

This paper introduces a new generic platform for onboard payload signal processing. The system is built up around an NoC with a bridge to an AMBA system which supports easy integration with existing AMBA based platforms. With the use of a pthreads interface the platform allows for simple programming and easy extension. For prototyping purposes, an implementation has been made on an FPGA together with a range of I/O options to assess its capabilities. SpaceWire and other interfaces support the extension of the demonstrator platform across multiple boards and allow to connect it to onboard networks and systems. This paper shows that novel and established chip architectures can be integrated in a way that combines their benefits, and represents a promising candidate architecture for future on-board processing platforms. © 2011 IEEE.

关键词： Signal processing

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